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Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into...
Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these techniques have relatively poor coverage of the timing critical paths. We propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate...
In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Pseudo functional test patterns targeting the longest paths captured by each flip-flop are first generated. To determine the sensitivity to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level...
This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.
This paper discusses power system fault simulation/modeling aspects on protection and control performance, requirements and technical problems often occurred during relay testing and commissioning, analyzing testing conditions, protection schemes and solutions for power systems, discussing major factors to be address during fault simulations in order to have successful outcomes for relay testing and...
An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods.
This paper describes an innovative test approach to validate an anechoic Compact Range antenna indoor chamber. It documents the antenna chamber mmW characterization efforts and results for the Lockheed Martin Mission Systems & Training (MST) antenna chamber CR1 in Owego NY. The mmW characterization results indicate that the chamber amplitude performance is better than 0.8 dB RMS, and the chamber...
It has been mathematically shown that the testing problem is NP complete. Numerous attempts have been made in creating and designing algorithms to successfully test a digital circuit for all faults in computational linear time. However, due to the complexity of the NP problem, all these attempts start becoming exponential with an increase in circuit size and complexity. Algorithms have been proposed...
A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together...
With the high costs associated with modern IC fabrication, most semiconductor companies have gone fabless, i.e., they outsource manufacturing of their designs to contract foundries. This horizontal business model has led to many well documented issues associated with untrusted foundries including IC overproduction and shipping improperly or insufficiently tested chips. Entering such chips in the supply...
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