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A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together...
Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into...
This work presents a method to measure the frequency of an on-chip test clock in relation to a reference clock. Frequency measurement is accomplished by counting pulses of both test and reference clocks, albeit adjusting the reference clock pulse count to estimate the number of pulses that the test clock is expected to see. The proposed method places no constraints on the frequency relationship between...
This paper describes an innovative test approach to validate an anechoic Compact Range antenna indoor chamber. It documents the antenna chamber mmW characterization efforts and results for the Lockheed Martin Mission Systems & Training (MST) antenna chamber CR1 in Owego NY. The mmW characterization results indicate that the chamber amplitude performance is better than 0.8 dB RMS, and the chamber...
This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates...
Cell-aware faults have previously been proposed to more effectively detect defects within gates. At the same time, n-detect test sets that provide multiple detections of each stuck-at fault are often used to maximize the detection of unmodeled defects. However, n-detect test sets are often not particularly effective at fortuitously detecting all untargeted cell-aware faults. In this paper, we investigate...
This paper discusses power system fault simulation/modeling aspects on protection and control performance, requirements and technical problems often occurred during relay testing and commissioning, analyzing testing conditions, protection schemes and solutions for power systems, discussing major factors to be address during fault simulations in order to have successful outcomes for relay testing and...
With the high costs associated with modern IC fabrication, most semiconductor companies have gone fabless, i.e., they outsource manufacturing of their designs to contract foundries. This horizontal business model has led to many well documented issues associated with untrusted foundries including IC overproduction and shipping improperly or insufficiently tested chips. Entering such chips in the supply...
In this paper, a new adaptive computing fabric (ACF) that achieves both real-time multi-mode/multi-rate adaptation and lower error floor for cognitive SoC applications is presented. The VLSI architecture of the ACF is experimentally shown to meet the DVB, 802.3an and 802.ad target specifications. Our design delivers a 10-14 bit error rate (BER) with a bit energyto- noise density of Eb/N0=5dB with...
An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods.
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