A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-&#x03BC;m CMOS

Chun-Yu Lin; Tun-Ju Wang; Tsung-Hsien Lin

doi:10.1109/ASSCC.2017.8240264

A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS

Lin, Chun-Yu, Wang, Tun-Ju, Lin, Tsung-Hsien

Source

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 253 - 256

Abstract

This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC 0.18-pm CMOS technology. The core area is 0.467 mm². The chip dissipates 11.1 mW from a 1.8-V supply voltage.

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book e-ISBN :	978-1-5386-3178-2
DOI	10.1109/ASSCC.2017.8240264

Authors

Lin, Chun-Yu

Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

Wang, Tun-Ju

Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

Lin, Tsung-Hsien

Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

Keywords

Phase locked loops Calibration Delays Clocks Electromagnetic interference Frequency modulation

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Data set: ieee

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IEEE

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Lin, Chun-Yu

Wang, Tun-Ju

Lin, Tsung-Hsien

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A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS