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In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to...
This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area...
Resistive RAM (ReRAM) is an attractive candidate for next generation embedded nonvolatile memory [1][2], with several advantages compared to conventional flash technology. First, ReRAM is a CMOS-compatible low temperature back-end of line (BEOL) memory. There is almost no mutual impact between ReRAM element and front-end CMOS devices during the wafer processing. Second, it only needs 2∼4 extra masks,...
An effective method is proposed to reduce dynamic power for synchronous 2-read/write (2RW) 8T dual-port (DP) SRAM. Adjusting the wordline (WL) pulse timing control circuit is newly introduced for both reading and writing operations. Row addresses of port-A and port-B are compared. The same row access is detected or not in each cycle, which is an inherent access mode of 2RW 8T DP SRAM. In different...
This paper provides details on the new Broadwell server product family designed on 14nm Intel process. This was the first Xeon® server product on this process node. Low power, density optimized product, Broadwell-DE, has upto 8 dual-threaded 64b Broadwell cores [1], 12MB L3 cache, 2 10GT/s Ethernet KR lanes, 2 DDR4–2400MHz memory channels and 24 8GT/s PCIe lanes. Broadwell-SP, a high performance server...
This paper presents a high performance dual-axis (pitch and roll) MEMS vibratory gyroscope readout ASIC which converts angular rate information to digital output. Two signal processing chains surrounding the MEMS sensor are implemented, namely the drive channel and the sense channel. The drive channel drives the sensor to resonate at its resonant frequency, which produces a velocity of the sensor...
This paper presents a new concept of PUF based on a chaotic behavior. Chaos is essentially not a random phenomenon but a deterministic non-periodic flow which can be utilized to extract reproducible unique ID entropy. The strong parametric sensitivity of the chaos guarantees ID variety and unclonability over unpredictable manufacturing variations. An undesirable disturbance due to dynamic parametric...
This paper presents an integrated wireless multiple sensors System-on-Chip (SoC) for healthcare including 3-lead ECG, bio-impedance (Bio-Z), and body temperature. To allow continuous and real-time monitoring, the SoC has included a multi-channel reconfigurable QPSK/BfSK transmitter (TX) to accommodate different power-constraint conditions. Fabricated in 130nm CMOS technology with a total die area...
This paper presents a 16-channel analog front-end (AFE) for wearable dry EEG recording. A novel AFE architecture that combines time division multiplexing (TDM) and chopping stabilization (CS) to improve the system common mode rejection ratio (CMRR) and the input-referred noise is proposed. With TDM, the reference electrode is connected to single channel input during its time slot to avoid the CMRR...
In this paper, an amplifier-less digitally-controlled lithium-ion (Li-Ion) battery charger is presented. Owing to the digitally-controlled technique, the proposed charger eliminates all analog circuits and reduces the size of the power transistor. Hence, the proposed charger features a simple circuit structure and a small chip area. Additionally, this charger provides essential operations including...
A 0.5-V BJT-based thermal sensor design is first demonstrated in a 10-nm CMOS. A charge-pump technique is proposed for operating with a digital core supply voltage as low as 0.5 V without the restriction on forward junction bias (∼0.7V). A switched-capacitor integrator loop is presented for process-insensitive voltage-to-frequency conversion. This thermal sensor achieves an RMS resolution of ±0.173°C,...
This paper presents an ultra-low power 32.768-kHz fractional-N phase-locked loop (PLL). Several circuit techniques are adopted to facilitate low-power operation. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a near-off switch is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore,...
This paper presents a 15-bit ΔΣ ADC with 10kHz-BW which can handle 30V CM voltages with high AC CMRR (in excess of 115dB at 10kHz) while operating from a 1.8 V supply. An HV capacitively-coupled chopper at its input enables the accurate sampling of input signals beyond the supply rails. Chopping is used to mitigate the ADC's offset and to enhance its CMRR, especially at high frequencies.
An energy-efficient self-charged crystal oscillator (SCXO) employing a quadrature-phase shifter is proposed to provide wide-range pulse injection timing for power consumption reduction. The passive resistors of quadrature-phase shifter can be shared by the startup circuit to save area consumption. The double-edge extractor and the low-power comparator are added to reduce the power consumption. The...
An area-efficient CTDSM for sensor applications is presented. The proposed capacitively-coupled CTDSM combines the functions of precision amplifier and DSM to achieve hardware efficiency. The 1-bit quantizer with FIR-DAC improves the linearity without using DEM in multi-bit architectures or large-size analog filters. The proposed currentsplitting OTA saves the capacitor area in the first integrator...
This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling scheme to increase the data rate. It is the most useful in battery-powered IoT applications where both energy and silicon area are critical constraints. The capacitive coupling effect with all digital circuit allows our design to operate...
An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL) with switching-independent power profile is used to yield intrinsic resistance against Differential Power Analysis (DPA) attacks with minimum area and energy consumption. Measurement results show that this 0.048mm2 core achieves energy consumption...
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