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Field-programmable gate arrays are attractive can-didates for wireless applications due to their reconfiguration capability and high performance development. However, sub-threshold leakage power in modern FPGAs has become a critical obstacle for these devices in entering to this application domain. Subthreshold leakage current of programmable interconnections is responsible for most of the static...
Static Random Access Memory (SRAM) Compiler is the silicon compiler that generates SRAM IP cores with various specifications. A high performance and flexible SRAM compiler is proposed in this paper. Our compiler uses block assembly techniques with uniform physical data syntax. This encapsulates the compiler from low level module information. Hence it is self-adaptive to the migration of technology...
With ever increasing power density and temperature variations within chips, it is very important to correctly model temperature effects on the devices in a compact way. In this paper, it is first shown that the temperature dependencies of the mobility and the saturation velocity need to be treated separately in modeling the current with temperature effects. Then, a new compact temperature-dependent...
A floating millivolt reference circuit to generate a PTAT current was developed by using MOSFETs operated in the subthreshold region. The circuit generates a floating voltage of about 10 mV. The variations in the reference are ?2.7 % in a temperature range from 20 to 100 ?C. The accuracy of the reference circuit can be improved to ?0.3 % with a correction technique using a curvature-correction circuit...
Given a particular digital logic path and a desired operating frequency there exists an optimal trade off of dynamic, static, and short-circuit power dissipation. Techniques like DVS and variable thresholds exist to bring paths closer to this optimum, but intrinsic complications limit how close they can get. We present capacitively-biased, floating-gate CMOS (FG-CMOS) as a new, and intrinsically more...
Power Clock Generators (PCGs) are the prevalent overhead for the adiabatic systems and mutilate all the low-power advantage from the adiabatic logic part by consuming a large portion of the total power in the clock generation circuitry [1]. In addition to the PCG issues, routing multiple clock phases for adiabatic circuits is not very convenient and raises a number of cost, performance and viability...
System-on-a-chip with multiple power domains reduces leakage power consumption by power gating which shut off the idle blocks. Power gating is an effective technology to reduce sub-threshold leakage current. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and make the technique not worth the effort. For example, power gating...
This paper presents eigenvector algorithms (EVAs) for blind deconvolution (BD) of multiple-input multiple-output infinite impulse response (MIMO-IIR) channels (convolutive mixtures). Using the idea of reference signals, the EVA is derived. Differently from the conventional researches on EVAs, one of the novel points of the paper is that the EVA using any reference signal is applied to the BD problem...
Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to handle highly complicated recognition tasks. We describe a multi-SIMD architecture and the design of a vision processor based on it for carrying out such difficult image recognition tasks. The proposed architecture consists of two...
This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the proposed virtual cluster will have advantages of (1) reduced forwarding complexity in the processor datapath, (2) improved programming model for further code...
Some of autors proposed the blind equalization algorithm for communication systems. In the algorithm, we realize higher reliability of the recovered signals and faster convergence rate of the algorithm, because the parameter included in Sato cost function is adjusted by using both outputs of the equalizer and the decision device. However, we cannot apply this method to communication systems except...
Reducing cache misses without increasing cache associativity is critical for reducing the power consumption and cache access time. This paper has focused on the stack of a program which often occupies more than half of total memory accesses [1]. This paper, as a result, proposes so-called dynamic stack allocation where the stack pointer is shifted at run time to a memory location which is expected...
Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java virtual machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable...
Thermal characterization of ICs and on-chip temperature monitoring have become key tasks in electronic engineering. In this paper, we present the design of an on-chip CMOS temperature sensor based on the temperature dependent characteristics of the subthreshold current. The proposed sensor achieves high accuracy sensing (0.56?C maximum error), wide temperature range (25-90?C), and extremely low area...
This paper presents a novel interface for ion-sensitive field effect transistors (ISFET) in which operation at a fixed electrical bias is achieved by voltage clamping. The chosen topology provides pH-dependent current and voltage output signals to drive an appropriate output stage. The circuit can be operated in either strong or weak inversion, depending on the requirements of the application with...
The paper presents a contrast retina microchip that provides its output as an AER (address event representation) stream. Contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffusive network. This current based computation produces a large mismatch between neighboring pixels, because the currents can be as low as a few pico amperes...
To quantify cellular toxic responses to drug treatment or environmental stresses such as nanoparticles, a high throughput imaging modality with automated image analysis protocol is applied. Fluorescence images from human H4 neurogliomal cells exposed to different concentrations of CuO nanoparticles were collected by a high content fluorescence microscopy. A fully automated fluorescent cellular image...
Many works investigated the phenomenon of lava flow through numerical models, obtaining excellent results, although most of the models require several approximations. Each model, in fact, has its restrictions: for instance, some of them work only on inclined planes, while others do not consider cooling processes associated to lava flow and so on. Simplifications are often needed to afford the computational...
H.264 and AVS are the two latest video coding standards. Since the similarity between their structures, it is feasible to develop a dual-mode VLSI decoder for supporting both standards, with substantially less cost than the solution with two individual decoders. In this paper, we propose a dual-standard VLSI architecture for MC interpolation, which is the most calculation intensive module of the dual-mode...
In this paper, we present a high performance memory cache based motion compensation architecture for H.264/AVC HDTV decoder. To solve the bottleneck of memory bandwidth for H.264/AVC HD applications, three combined bandwidth optimization strategies are proposed to minimize the memory bandwidth for MB-based decoding. To improve the interpolation hardware utilization and reduce the interpolation cycles,...
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