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InGaAs-OI and GeOI SRAM cells using optimized threshold voltage (Vt) design to enhance the intrinsic variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6T SRAM cells are presented. For low-voltage SRAMs operating at low Vdd, low-Vt design shows smaller variability while the design trade-off between performance and leakage should be considered. For highperformance...
We report an experimental study of the carrier transport in long channel tri-gate (TG) and omega-gate (ΩG) Si nanowire (NW) transistors with cross-section width down to 10 nm. Electron and hole mobility have been measured down to 20 K. We discuss the influence of channel shape, channel width and strain on carrier mobility. In particular we have shown that transport properties are mainly driven by...
Standard cell libraries are designed focusing on the best performance-area trade-off for a technology at nominal supply. Scaling supply voltages emphasizes the effects of systematic or random variation. We revisit existing approaches and present two new design points in standard CMOS that target variability hardened standard cells integrated into the digital design flow. They are optimized for dynamic...
In this paper, the feasibility of High-k/Metal Gate (HKMG) Replacement Metal Gate (RMG) stacks for low power DRAM compatible transistors is assessed. It is shown that traditional RMG gate stacks cannot be used because of the additional anneal needed in a DRAM process. New solutions are developed, and a PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations...
We present examples of deterministic solvers for the Boltzmann transport equation for electrons and holes in a 3D and quasi 2D fc-space. Compared to the standard approach, the Monte Carlo method, these deterministic solvers have certain advantages. They yield exact stationary solutions, which, for example, are required for the simulation of the floating body effect in SOI devices. They allow exact...
The impact of channel dimension and crystallographic orientations on ballistic transport of germanium junctionless nanowire transistors is investigated using 3D quantum-mechanical simulations and is compared with those of the inversion-mode nanowire transistors. Analysis of the contribution of source-to-drain tunneling to the off-current shows suppressed direct tunneling in the junctionless design...
Static and low frequency noise (LFN) characterrizations in densely packed single-walled carbon nanotube thin film transistors (CNT-TFTs) are presented. To this end, the Y function method (YFM) is employed for parameter extraction in order to alleviate the influence of the channel access resistance. The low field mobility (μ0), threshold voltage (Vth), mobility attenuation factor (θ) and on/off current...
For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for LG=20 nm), we hit a dramatic transition in transport mechanism from...
In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design...
Top-down ZnO nanowire FETs have been fabricated using mature photolithography, ZnO atomic layer deposition (ALD) and plasma etching. This paper investigates the effects of oxygen adsorption by measuring FET characteristics at different gate bias sweep rates and by characterizing hysteresis effects. Unpassivated devices exhibit a low threshold voltage shift of 5.4 V when the gate bias sweep rate is...
The scattering mechanisms limiting the electron mobility in Si(110) MOSFETs have been studied in function of the temperature. They have been compared to the ones limiting the electron mobility in Si(100) MOSFETs. It appeared that the lower electron mobility encountered for the (110) orientation was coming from a stronger limitation due to the sole Coulomb and surface roughness scatterings. Indeed,...
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
We have revealed that, using an originally-developed noise measurement system, the change in 1/f noise intensity due to a substrate bias mostly ranges in low frequencies, from 1 Hz to 100kHz. Above 100 kHz to 30 MHz, the 1/f component still continues. However, the noise intensity does not strongly depend on the substrate bias. The substrate bias alters the distance of inversion carriers from the SiO...
A new microfabricated device for heating and sensing in gases is presented. It is based on the resistive heating of a micro- or nano-metric hollow cylinder of titanium nitride, and measurement of its (temperature-dependent) resistance. This article presents the fabrication and temperature calibration of the device, and illustrates its function as flow meter and thermal conductivity meter. A temperature...
Aluminum-Induced Crystallization is applied on crystalline Si substrates. By this method a physical-vapor-deposited amorphous Si layer is successfully transformed into a monocrystalline solid-phase epitaxy (SPE) p-doped layer at an anneal temperature of 400°C. The as-grown epitaxial layer takes on the orientation and the lattice constant of the substrate. It is shown that a complete coverage over...
A new parameter extraction methodology based on split C-V is proposed for FDSOI MOS devices. To this end, a detailed capacitance theoretical analysis is first conducted emphasizing the usefulness of the Maserjian function. Split C-V measurements carried out on various FDSOI CMOS technologies show that the Maserjian function exhibits a power law dependence with inversion charge as ∝ Qi−2 whatever the...
Novel Deep Trench Buried-Body-Contac (DBBC) has been successfully developed for 4F2 DRAM cells on sub-30nm technology node. The critical requirements of thermal stability, shallow junction depth, and conformal source-drain doping profile for the contact are achieved by using an ultra thin Ti silicide ohmic layer and PLAD technique, which also show excellent electrical performance and process feasibility...
Complementary lateral-drain-extended MOS transistors (CLDMOS) were integrated in a 0.13 μm SiGe BiCMOS technology. The LDMOS devices were realized in the dual-gate-oxide CMOS process without additional process steps. Drift regions were formed by the lightly-doped drain (LDD) implantations of 3.3V NMOS and PMOS transistors of the baseline process. The NLDMOS transistors use a combination of n-LDD and...
Dimensional scaling will continue in Si CMOS technology which will extend to beyond 10nm. Key challenges for dimensional scaling and expansion of silicon-based technologies as well as research directions will be reviewed in traditional semiconductor applications such as DRAM, NAND Flash, logic as well as advanced devices including STT-MRAM, ReRAM and reconfigurable logic. Furthermore, other areas...
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