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For past 10 years Advanced Driving Assistance System (ADAS) has rapidly grown. Recently not only luxury cars but some entry level cars are equipped with ADAS applications, such as Automated Emergency Braking System (AEBS). The European New Car Assessment Programme (EuroNCAP) announced its introduction of AEBS test from 2014, which will accelerate the penetration of ADAS in Europe. Also DARPA challenge...
Potential of a cloud system combining a smart device and cloud servers is increasing. One of the representative examples is "Siri" which offers a friendly web knowledge navigator based on natural language user interface. Since latest portable devices equip not only a microphone but also a high resolution camera, this kind of cloud based framework is also promising to create various kinds...
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show...
Mapping of Intellectual Property (IP) cores onto Network-on-Chip (NoC) architectures is a key step in NoC-based designs. Energy, bandwidth, and latency are the key parameters that need to be optimized in such designs. In this paper, we propose Centralized 3-D Mapping (C3Map) using a new octahedral traversal technique and Attractive-Repulsive Particle Swarm Optimization (ARPSO) based algorithms for...
This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power...
A 10-bit successive approximation ADC for low voltage and low power applications is proposed in this paper. The chip operating voltage is 0.7 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayered sandwich capacitor array is used in the digital to analog converter employed in the ADC to reduce the overall capacitance value and power consumption effectively. The proposed...
Smart sensors are currently demanded in various kinds of applications to pave a way for better life. To reach this goal, it is necessary to provide energy-efficient solutions with analysis capability. Though state-of-the-art SoC's can meet μW-level processing requirements, front-end sensors remain a bottleneck to be solved. In this paper, a few sensors based on event-driven techniques to improve energy-efficiency...
Many people predict Internet of Things will become the next big wave of IT industry. Some people predicts there are a trillions of dollars businesses in the IoT era, as IoT will significant improve our lives. However, are energy efficiency VLSI designs critical to the success of IoT? Or, they are just nice-to-have. In this talk, we plan to discuss the following topics: What are the key computing and...
The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because of die stacking and different thermal conductance between layers. Up to now, most previous works cannot further achieve thermal balance of the 3D NoC systems since they consider either only temperature or only traffic information. We propose a Proactive Thermal-Dynamic-Buffer Allocation (PTDBA) scheme...
In this paper we address the problems of mapping (spatial distribution) and scheduling (temporal distribution) of tasks of an application over multiple computational units or cores. Algorithms for these are chiefly of two kinds — one, mapping followed by scheduling and two — unified mapping and scheduling. In this paper, we explore a new network topology based on Projective Geometry (PG). We develop...
The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. Because of the die-stacking architecture, the thermal problem becomes more severe than in 2D NoC. To simultaneously consider the thermal safety and system performance, proactive thermal management (PDTM) has been proved as an efficient way to control the system temperature against overheat...
As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection,...
In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel...
As technology node advances, Extreme Ultraviolet Lithography (EUVL) is regarded as the most promising technology for improving the lithographic printability. However, there are still several challenges in EUVL like the most critical flare effect that causes patterning distortions. As a result, dummy Alls are added to a layout (i.e., dummification) to compensate the flare effect. Although dummy fills...
This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance...
An integrated boost converter with maximum power point tracking for solar photovoltaic (PV) energy harvesting has been proposed. The maximum power point tracking (MPPT) function is realized with analog circuits, instead of using a microprocessor. In the proposed chip, the output power of the PV modules is controlled by modulating the on-time of the boost converter. The chip was designed and fabricated...
Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method...
The CMOS PA becomes a reality due to the active research work in recent years. But the performance is not up to the expectation because of the inherent problems of CMOS such as low power density and poor linearity. To enhance the performance further, various adaptation techniques are applied to CMOS PA, i. e. at the gate and drain. In this talk, we will introduce the advanced CMOS PA with the adaptaions.
Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This...
The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g., the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction...
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