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Self-timed circuits have the unique properties of a lack of competition. One of the main problems of such circuits design — the analysis on self-timing (elements switching) and the construction of large circuits. In traditional approach computational complexity is so great, that it does not allow to analyze the most important practical circuits. In the functional approach we propose hierarchical method:...
In this paper we have proposed a fault-tolerant scheme based on totally self-checking system with low overhead. The scheme has only one self-checking module and another one is simplex module (combinational circuit). The analysis of the reliability of proposed scheme is given.
The novel approach to functional verification of memory subsystem components of multicore microprocessors with multilevel memory organization are considered in this paper. Some benefits of application standalone simulation based verification are marked out. The approach is based on application of high-level memory subsystem model of microprocessor full-system simulator. It allows to build UVM based...
A survey on various method of extracting small signal and large signal models parameters for GaN HEMT is presented. Small signal parameters are calculated from measured s-parameters, and a large signal model is derived by introducing additional nonlinear lumped elements to the small signal model. The transistor model is analyzed as the complex of the extrinsic and intrinsic model. Intrinsic parameters...
The paper presents an architecture of a Hybrid Active Noise Control (ANC) system, which is a combination of the Feed-Forward (FF) and Feed-Backward (FB) ANC systems. A modification of the ANC system, known for the FF case only, is extended to the Hybrid ANC system. The modification allows to accelerate the adaptation process, if the gradient search based adaptive filtering algorithms, like Least Mean...
In this paper, we discuss how a software ABC can be effectively used to derive distinguishing sequences for Verilog-descriptions. A set of these sequences can serve as a test suite for a digital device that is designed based on the corresponding Verilog-description using the FPGA technology. The paper contains a methodology for such test derivation technique, as well as technical details about the...
Yaliny is a company whose aim is to create a satellite communication system with a new level of performance. It is planned that the system will, having been fully deployed, provide communication services and fast Internet connection to any customer all over the Globe. The system is designed so that its link budget will allow having up to several million users all over the world utilizing the network...
For System-on-Chips (SoCs) one of the most critical design constraints is power consumption. This paper presents memory built-in self-test (BIST) grouping methodology which takes into account the given peak power, power domains based on Unified Power Format (UPF) and optimal test time. The mentioned grouping criteria enable to perform power-aware memory BIST design at early stages of SoC design. To...
The paper presents the results of the investigation of the adaptive algorithm for power amplifiers linearization. The basis for this algorithm is a method of adaptive inverse control of the objects such as «black boxes». Algorithm uses the Least Mean Square criterion. Computational procedures may be an alternative or complementation to LUT of amplifier input signal predistortion. The results of computer...
Cyber physical system Smart Cyber University (CyUni) is characterized by the following: the presence of the digitized space of regulatory rules, accurate and active cyber monitoring scientific and educational processes, automatic generation of operational actuator's actions, independent cybernetic resolving to manage financial and human resources, and excluding the paper carriers from production processes...
The authors consider the built-in self-test signature model. This article describes the analysis shows the ability of signature schemes, as well as the synthesis of the test generator. The approach is generalized for the case when for the synthesis of the test we use several registers with a common synchronization. Experiments have shown that the method of signature generation circuit design allows...
In this article the features of sum codes for error detection in data vectors are discussed, that is of interest at the time of concurrent error detection (CED) systems organization. The article describes a classic sum code (Berger code), as well as weighted data bits sum code. It includes the method of code formation, that is optimum with regard to error detection in data vectors. This code has the...
Speed-independent fused multiply-add unit as a coprocessor is represented. It purely conforms to IEEE 754 Standard. For minimization hardware and power consumption, a number of pipeline stages is reduced down to two. Wallace tree in the multiplier utilizes redundant self-timed code. Represented unit is developed on a base of standard 65-nm CMOS bulk process. It provides a performance up to 0.54 Gflops,...
"Quantum " data structures for synthesis of digital system are proposed. They are based on transactions between addressable memory components to implement any functionality. The new approach of logic function minimization for synthesis of digital systems is proposed. It is supposed to apply vector form (quantum) of description logic and sequential structures implemented into memory elements...
Network-on-Chip (NoC) was introduced as a promising paradigm that can respond to the problems inherited from bus-based systems. In the general case it is better to design specific topology instead of regular for effective use of chip resources. This paper presents a technique for automated design of the custom Network-on-Chip topologies and a CAD subsystem implementing it.
In this article the study of characteristics of modular sum codes for error detection in concurrent error detection (CED) systems is presented. The article provides the classification of sum codes with arbitrary modulus values. It also gives the definition of common patterns in detection ability of all modular sum codes. Determined characteristics of modular sum codes are supported by the results...
Rapidly developing FinFET technology, alternative to the conventional planar technology, plays an important role in routing modern silicon industry. Due to unique structure of FinFET transistors the defect types and resulting fault models is different for FinFET transistors compared to planar ones. As a result the well-established flow used for embedded test and repair solutions development for MOSFET-based...
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