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This paper presents a 60 GHz Gilbert-cell down-conversion mixer in 130 nm RF CMOS technology. In order to enhance the mixer gain and noise performance, inter-stage inductors are used between the switching pairs and the transconductance stage. Also, for the same purpose, the current bleeding/injection technique is adopted which allow us to control both the Conversion Gain (CG) and Bandwidth (BW). Due...
It has been made clear that the presence of hot carriers triggers a series of physical processes that affects the FD-SOI and FinFET device characteristics under normal circuit operation. These effects cumulatively build up over prolonged periods, causing the circuit to age with time, resulting in performance degradations that may eventually lead to circuit failure. In this paper we tackle with the...
Positron emission tomography (PET) has gained interest as one of the most reliable techniques for in-vivo range monitoring in particle therapy. The INSIDE project uses a new SiPM based PET implementation that processes individually each single photon acquired by two detector plates placed close to the patient. In order to detect coincidences in the single photons stream, a fast sorter architecture...
This paper describes the design of resonant coil and receiver IC for wireless power transfer (WPT) based on magnetic resonance method in mobile device. The coil is modeled and optimized based on magnetic simulation tool to obtain maximum power transfer efficiency. The fabricated receiver IC consists of rectifier, DC-DC converter and charging control circuit is designed to reduce the power loss in...
In this work, the implementation of a static memory grid, consisting of sectors with size 256×8 bits, is presented. The grid supports memory write speedup leading to a minimized write pulse of at least 5 times than the typical implementation of static memories. All implementations have been done using the CeidMem Static Memory Library and the simulation results of the behavior of the grid is presented...
In this paper, a new model based on piecewise linear (PWL) functions is proposed and analyzed by considering the well known Pernarowski's mathematical model for an isolated beta cell. Contrary to Pernarowski's model, we replace the original cubic functions with PWL functions with multi-segments in order to obtain bursting electrical activity (BEA) of beta cell. The number of segments depends on the...
Thanks to their ability to store information in a continuous (analog) form, memristors are termed as well-suited for several real-time signal processing tasks. In this context, here we present a memristive circular buffer, using memristor and its multi-bit storage ability to temporarily store encoded information in a compact form, thus improving the area performance as well as the delay and energy...
The IEEE P1619 standard was developed to protect data in shared storage media. Most of the works that have been presented until now have adopted a no robust scheduling scheme to implement various architectures. At first, an exploration on P1619 applicability is being made and then a different scheduling approach, compared to the typical one which exists in literature, is being proposed. The architectures...
High-level synthesis is the technique that translates high-level programming language programs into equivalent hardware descriptions. The use of conventional programming languages as input to high-level synthesis is challenging, due to the conceptual differences between software programs and hardware descriptions, but is nonetheless becoming the preferred input to high-level synthesis tools. Compilers...
The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This...
In this brief, the design and the experimental behavior of a memristor emulator is presented. An npn and a pnp transistor control the switching transition to the low resistance state in forward and reverse input bias, while a capacitor is responsible for the hysteresis loop. The circuit does not need external bias and in this sense it operates in a passive mode. The measured i-v characteristic exhibits...
An electronic design and evaluation tool for quantum circuit design is presented. It allows easy implementation of quantum algorithms based on the circuit model of quantum computation. The layout of an ideal circuit network can be designed in the logical layer and then automatically get converted into an encoded form closer to the physical layer. The possibility to select and apply the desired quantum...
The study done in this paper concerns the use of a new control technique of current using adaptive hysteresis regulator by fuzzy logic on the command of a parallel active filter. For the proposed method, the hysteresis band is adapted in every moment in order to determine the switching frequency and control the position of the command pulses. This allows a better tracking of a heavily distorted current...
Conventional bit-flipping (BF) algorithms spectacularly fail to handle punctured LDPC codes as they use hard decisions and, therefore, they cannot effectively cope with zero-reliability punctured symbols. However, BF techniques lead to low-cost high-speed decoders. This paper introduces a novel method that enables the use of BF-based iterative decoders for punctured LDPC codes. An erasure preprocessor...
In this paper the performance of the 2D pixel clustering algorithm developed for the Input Mezzanine card of the ATLAS Fast TracKer system is presented. Fast TracKer is an approved ATLAS upgrade that has the goal to provide a complete list of tracks to the ATLAS High Level Trigger for each level-1 accepted event, at up to 100 kHz event rate with a very small latency, in the order of 100 μs. The Input...
In this paper, the experimental study and the related evaluation of the memristive behavior demonstrated by a simple device, a tungsten filament bulb, is presented. It was found that this device operates as a non-ideal memristor, demonstrating a Type-II non-crossing, pinched hysteretic loop, while the evaluation of experimental results clearly hints to assorting the type of this device as an extended...
In this paper, a novel architecture for wideband input impedance matching consisting of two common gate (CG) transistors is presented. One CG transistor is placed on top of the other in a current reuse fashion such that both transistors appear in parallel at the input. As a consequence, the transconductance requirement for input matching from each NMOS transistor is reduced to half compared to a simple...
The analysis, design and circuit synthesis of a fractional order switched system is presented in this paper. That system is capable of showing chaotic oscillations with a fractional order less than three, i.e., 2.4. The dynamical system is called fractional order unstable dissipative system (FOUDS); because it consists of a switching law to display strange attractors. Its dynamical behavior is explored...
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