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Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requirements and technical aspects which should be considered for successful circuit design involving capacitive MEMS. To illustrate the process, the design of an input stage for a MEMS dielectric...
An energy harvester operating at high temperature, up to T=300 °C, is presented. In particular, a voltage doubling rectifier realized with two 4H-SiC Schottky diodes is used to rectify the AC voltage output of a piezoelectric bimorph with a Curie temperature of TC=320 °C. The rectifier efficiency is of about η∼89% and it slightly increases with temperature due to the corresponding diodes threshold...
This paper presents a cascaded ultra low power LNA structure. The proposed architecture benefits from a common gate LNA as the first stage followed by indcutorless common source LNA. The complete design was implemented in a standard 130nm RF CMOS process. The design occupies 130µm × 130µm active area. The circuit operates at 2.4GHz and draws 240µm under supply voltage of 1.2V. It shows active voltage...
This paper presents a low noise CMOS circuit for precise reading of an array of magnetoresistive sensors. The settling time of the low frequency AC coupled amplifier defines the reading speed for the sensors, being usually very long due to the large time constants. We present a fast settling mechanism that momentarily reduces the resistance defining the high-pass filter pole and changes it back to...
This work presents a high dynamic range and high efficiency energy harvesting system for low power sensors architecture. The circuit has been conceived as a dual band architecture able to capture the largest amount of EM radiation available in the urban environment and to provide an autonomous device potentially with infinitive cycle of use. The device is tuned to receive both GSM and Wi-Fi frequencies...
Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for universal memory. An electrical model of STT-RAM cell is needed to adequately explore the design space of the device. In this paper, a comprehensive and compact Verilog-A behavioral model of STT-RAM cell is presented. The model captures both dynamic switching aspects and static properties of the magnetic tunnel junction (MTJ),...
This paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class-B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves...
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize...
Concerning the design of electrostatic kinetic energy harvesters, it is vital to be able to extract the greatest amount of power possible as the quantities obtained are typically quite small in comparison to other more developed power source technologies. In this article, we investigate the effects on the power generated of three of the more significant control parameters. These include the load resistance,...
This paper presents a continuous-time (CT) quadrature bandpass (QBP) ΔΣ ADC which is reconfigurable in terms of quantizer resolution, bandwidth (BW) and IF. It is designed for use in a low power low-IF multi-band transceiver system. In simulations the presented implementation in a 130nm RF CMOS process achieves a resolution of 10.5 bit. Additionally, a total power consumption of 2.3mW from an 1.2V...
In this paper, we propose and analyze two different stream ciphers based on a Skew Tent Map and a Modified Logistic Map respectively. In order to improve the randomness of these systems, a single method for increasing the period length of the generated sequences has been applied. The results prove that the randomness of these systems can be severally increased by using this method, making these systems...
Size and cost of a boost converter can be minimized by reducing the voltage overshoot and fastening the transient response in case of load transient. The presented technique improves the transient response of a current mode controlled boost converter, which usually suffers from bandwidth limitation because of its right-half-plane zero (RHPZ). The proposed technique comprises a load current estimation...
This paper introduces a new concept of liquid phase inkjet-based fabrication process for low cost, low range and high throughput Radio Frequency Identification (RFID) tags. In this research, passive chips have one pad on the top of the chip and the back of the silicon die (bulk) acting as the second pad. Such a chip can be delivered, using an inkjet-based process, onto one pad of an antenna instead...
Diamond and SiC are wide bandgap (WBG) materials which can be used to fabricate high power devices with improved performance. The combination of these materials into one single device is expected to bring some benefits, like a better thermal management with a corresponding increase in the operating power. Diamond films deposited by Chemical Vapor Deposition (CVD) can be doped with boron, making them...
A modified band-gap circuit capable of producing programmable output differential reference voltage is described. Analysis of the effects of the amplifier noise and offset on the reference voltage is performed, obtaining a compact formula of general validity. A prototype, based on a switched capacitor amplifier with continuous time output, has been designed using the UMC 0.18 um CMOS process. The...
In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The proposed process flow is used to fabricate a 4-layer chip stack using homogeneous CMOS memory chips. Electrical measurements are carried out to...
With the number of Internet of Things (IoT) devices expected to explode to over 20 Billion devices by 2020, it is vital that efficient communication technologies are used. While ideally a single technology would emerge to simplify deployment, in practice the varying power and bandwidth requirements of different devices has led to an industry split over communication technologies, and while a number...
A new wide-input dynamic range, 64-channels current-to-frequency converter ASIC has been designed and is now under characterization. This chip, nicknamed TERA09, has been realized to equip the front-end readout electronics for the new generation of beam monitor chambers for particle therapy applications. In this field, the trend in the accelerator development is moving toward compact solutions providing...
Extensive knowledge of the protection device's behavior under electrostatic discharge stress is mandatory to characterize protective elements and systems. This paper gives a brief overview on different electrostatic discharge protection concepts, including general considerations on diverting stress, trigger mechanisms, and their limitations. The protection approaches have to be selected in conjunction...
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