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ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency...
In advanced technology nodes, Bias Temperature Instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops on a critical path do not switch their logic values for a long duration. These inactive flip-flops in the circuit experience accelerated workload-dependent static-BTI stress. The aging effect of static...
In recent years, we have seen a surge of interest in neuromorphic computing and its hardware design for cognitive applications. In this work, we present new neuromorphic architecture, circuit, and device co-designs that enable spike-based classification for speech recognition task. The proposed neuromorphic speech recognition engine supports a sparsely connected deep spiking network with coarse granularity,...
In the approaching era of IoT, flexible and low power accelerators have become essential to meet aggressive energy efficiency targets. During the last few decades, Coarse Grain Reconfigurable Arrays (CGRA) have demonstrated high energy efficiency as accelerators, especially for high-performance streaming applications. While existing CGRAs mostly rely on partial and full predication techniques to support...
To consider QoS for resource-limited mobile systems, we introduce a fast preemption mechanism on GPUs. First, we involve a dual-kernel execution model to support fine-grained preemption, and a resource allocation policy to avoid resource fragmentation problem. Second, we propose a preemption victim selection scheme to reduce the throughput overhead while satisfying a required preemption latency. Evaluations...
In recent years, Deep Convolutional Neural Network (DCNN) has become the dominant approach for almost all recognition and detection tasks and outperformed humans on certain tasks. Nevertheless, the high power consumptions and complex topologies have hindered the widespread deployment of DCNNs, particularly in wearable devices and embedded systems with limited area and power budget. This paper presents...
Energy harvesting systems recycling energy from ambient environment for extended lifetime have been proposed to be the next step in the evolution of the Internet of Things. One of the largest challenges of energy harvesting is the insufficiency and instability of ambient energy sources. Unlike wireless distributed systems considered to date, frequent power failures need to be taken into account in...
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory (NVM) solution to implement on-chip caches and off-chip main memories for its high integration density and short access time, but it suffers from considerable write latency and energy overhead. Aggressively relaxing its non-volatility for write fast and write energy efficient memory subsystems has been quite debatable,...
To achieve better vision through a retinal prosthesis, over 1000 electrodes are preferable. When increasing the number of electrodes, we may be faced a critical issue associated with the interconnection of stimulus electrodes and lead wires with good mechanical flexibility. To access the issue, we have proposed and developed a smart electrode that consists of a stimulus electrode combined with a CMOS...
During package manufacturing process, open defects of power bumps may cause insufficient power supply and degrade the power network yield. This work presents a redundant power bump insertion method to ensure power integrity by considering the power bump yields. The proposed method can efficiently assign redundant bumps by accurately estimating the location of worst load yield and minimizing the amounts...
This paper presents the closed-loop neural disorder control concept and some design considerations. Two architectures of closed-loop neuromodulation for Parkinson's disease and epileptic seizure are proposed. One is a closed-loop deep brain stimulator, which meets the IEC 60601-1 standard. The other one is an implantable SoC for epileptic seizure control, which is verified by animal experiment.
Out of all the optical network-on-chip topologies, the ring has been proved to be far superior to its competitors: the contention-free all-to-all communications offer the lowest latency possible, while its clean physical design with few crossings and ring resonators provides unmatchable power results. The ring implements simultaneous communications by using a communication matrix that sets a distinctive...
Advancement of retinal neuro-prosthesis technologies has reached a point where multiple devices are now available clinically as a therapeutic treatment for degenerative disorders of the retina. Reported outcomes have typically fallen short of patient and researcher expectations, and true restoration of vision remains an elusive objective. Here, the state of the art in visual prostheses is explored...
Evolving medical technologies, including stimulators, infusion pumps, and neuropros-thesis, are addressing progressively a wide range of neurological conditions, bringing fresh hope to patients where other solutions have proven to be ineffective. In this context, brain-computer interfaces (BCIs), that allow interaction between neural tissue and an external device, have been developed for a many diverse...
In-memory computing platforms, such as Resistive RAM (ReRAM), offer natural advantage to data-intensive applications. The benefits of data locality and capability to perform native Boolean operations is exploited for significant performance advantage in multiple contexts ranging across neuromorphic computing, associative memory-based computing, arithmetic benchmarks and general-purpose programmable...
We reported a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. This paper details a design of the proposed cascaded PLL. In order to reduce power consumption of 2nd-PLL, a power-efficient latch for pre-scaler is proposed. 3rd-1st...
A current-integration-based CMOS amperometric sensor with a bacteria-sized (1.2 μm × 2.05 μm) electroless-plated microelectrode array for high-sensitivity bacteria counting is presented. For high-sensitivity bacteria counting with sufficient SNR, noise must be reduced because the bacteria-sized microelectrode can handle only small current on the order of nA. The proposed current integration can reduce...
Aiming at real-life problems, microrobotic systems have gained more and more attention. However, limited achievable performance of microrobotic system prevents it from carrying out complex tasks. Current research work propose customize designs for different applications and incorporate dedicated accelerator for high energy efficiency. However, not only such techniques require significant manual effort...
Galois field (GF) arithmetic is used to implement critical arithmetic components in communication and security-related hardware, and verification of such components is of prime importance. Current techniques for formally verifying such components are based on computer algebra methods that proved successful in verification of integer arithmetic circuits. However, these methods are sequential in nature...
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