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Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The Unified Power Format (UPF) defines the power intent & specifications of low power designs and it provides designers with efficient methodology for low power design flow. It is supported by most of the EDA tools in the implementation flow. At the same...
This experimental study reports ESD failure analysis of AlGaN/GaN HEMTs. Effect of MESA isolation, gate and parasitic MESA Schottky diode on ESD robustness is studied. Cause of snapback instability, multiple NDCs and transition from soft-to-hard failure are discussed. Unique leakage trends and cumulative nature of degradation are discovered. Post failure analysis reveals role of inverse piezoelectric...
Sense amplifiers provide amplification to the very small voltage change in the memory datapath in near-zero access time. The sub-micron technology demands high performance sensing at extreme noise margins. In this paper, a state of the art latch-type storage element is proposed to provide a strong positive feedback for the small change in the differential sense input. A well synchronized 4T controlling...
The advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs...
Serious flaws in conventional understanding related to current filamentation and failure in ggNMOS is addressed. The conventional theory is revisited with new physical insights toward current filamentation. Filament dynamics under electrical and thermal instabilities is discussed while correlating it with stress time and current, silicide blocking and S/D doping.
Digital Microfluidic Biochip (DMFB) consists of Two–Dimensional (2-D) microarrays that can perform many diagnostic tests simultaneously. DMFB's are expected to be combined with cyberphysical systems in near future. Thus faster and error-free synthesis techniques need to be implemented on such chips. Synthesis of various bio-protocols is generally performed based on various mixing modules present on...
Fast downscaling of technology features in CMOS fabrication processes have resulted in numerous insurmountablechallenges, which prompted researchers to explore alternativestorage and computing technologies. Resistive RAM (ReRAM) isa promising non-volatile storage technology with high endurance, high retention capacity and compatibility with CMOS manufacturing flow. More importantly, ReRAM devices...
This paper proposes an alternate switched-capacitor amplifier capable of handling rail-to-rail input common-mode voltage without using a rail-to-rail op-amp. Unlike most existing switched-capacitor architectures, the proposed alternate architecture holds the op-amp input terminals at a fixed voltage level in both the sample and hold phases irrespective of the input signal common-mode voltage. Designed...
Ring oscillators are very popular process monitors due to its easy implementation and high sensitivity to process parameters. This paper presents a technique to accurately estimate the absolute threshold voltage Vth of device under test (DUT) using a reconfigurable ring oscillator (RO). Conventional techniques exploit NMOS-pass transistor based RO to estimate the Vth. However, the RO frequency includes...
A CMOS bandgap reference (BGR) circuit with low mismatch spread is proposed. A conventional BGR circuit uses a CMOS error amplifier and its input offset causes large spread in the bandgap output voltage. The proposed BGR circuit does not use a separate error amplifier. Instead, the bipolar transistor pair used to generate ΔVbe acts as input differential pair as well resulting in low mismatch spread...
Formal verification techniques for System-on-Chips (SoCs) have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logic and temporal relationships. The purpose of this paper is to show how this knowledge can be leveraged to optimize the dynamic power consumptions of SoC...
Limiting overall scheduling overheads (primarily combining task migration overheads and task selection overheads) is of utmost importance in today's resource constrained multiprocessor real-time embedded systems because it provides premium spare processor bandwidth that may be useful in various situations. This paper presents Migration Aware Low Overhead ERfair Scheduler (MALOES), a hard real-time...
The Physically Unclonable Functions (PUFs) are used in numerous security applications such as device authentication, secret key generation, FPGA intellectual property (IP) protection, and trusted computing. In this paper, compact implementations of Ring oscillator-based PUF (RO-PUF), Arbiter-based PUF (A-PUF) and RS Latch-based PUF (RS-LPUF) on an FPGA (Field Programmable Gate Array) platform are...
This paper describes the CMOS implementation of the variable output voltage, multi-phase switched capacitor step-up DC-DC converter with SAR-based regulation scheme. The number of target voltages generated using n-flying capacitors is of the order of 2n. A scheme for selection of switch is presented. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency...
Power analysis attacks use power dissipation to find the secret key of cryptographic devices. Two of the main techniques used as the countermeasures of power analysis attacks are masking and balancing. This paper considers countermeasures with balancing only. All balancing methods proposed so far require a pre-charge (or a pre-clear) state for all registers in which the logic is initialized to logic...
In this paper, a metaheuristic based on the hybrid of particle swarm optimization technique and simulated annealing scheme with Levy flight (l-HPSO) is proposed. The optimization technique incorporates Levy flight principle to improve convergence. Particle swarm optimization (PSO) is applied to construct initial solutions for simulated annealing (SA) scheme and these initial solutions are used to...
Repeaterless low swing interconnects have been proposed for enhancing the performance of long on-chip inter-connects. Synchronization of these high speed, low swing inter-connects is important for proper operation. This paper discusses a clock synchronizing circuit for low swing interconnects. The circuit uses a combination of a delay locked loop (DLL), that generates multiple phases of the clock,...
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