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Provides a brief professional biography of each keynote presenter. The complete presentations were not made available for publication as part of the conference proceedings.
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
Welcome to COOL Chips 20, an international symposium that provides you with the latest developments on low-power and high-speed chips. This year we are bringing you an exciting program that includes four keynote speeches, two instructive special invited lectures and one panel discussion in this noble harbor city of Yokohama.
Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes...
On behalf of the advisory committee of COOL Chips 20, I extend greetings to each of the conference attendees. This year we celebrate the 20th anniversary of this conference series that is part of the premier conference series on microprocessor architecture and technology and software. Today we have issues in cloud computing, cyber security, IoT, Big Data, and artificial intelligence, especially deep...
This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while...
An energy-efficient deep learning processor is proposed for convolutional neural networks (CNNs) and recurrent neural networks (RNNs) in mobile platforms. The 16mm2 chip is fabricated using 65nm technology with 3 key features, 1) Reconfigurable heterogeneous architecture to support both CNNs and RNNs, 2) LUT-based reconfigurable multiplier optimized for dynamic fixed-point with the on-line adaptation,...
Modern memory systems are equipped with multiple channels to achieve a higher memory bandwidth. Since the multi-channel memory system focuses on achieving a high memory bandwidth, data are allocated to all the channels. Hence, when the memory system is accessed, all the channels are activated until the next DRAM refresh starts. Therefore, when executing compute-intensive applications that do not need...
The advance of CMOS process is still going, but the end is coming into sight. Semiconductor chips with advanced process later than 21nm are so expensive that they are developed only for million selling products. On the other hand, the advanced AI, IoT and big data technologies require more and more computation/communication power with a tightly limited power budget. How we can develop a “Cool chips”...
This paper proposes a hardware accelerator, named IBE (Intelligence Boost Engine), to process both sensor fusion and machine learning algorithms for the Standing-egg SLH200 sensor hub SoC. The IBE is designed to have both efficiency and flexibility to support various emerging applications for future sensor hub SoCs in addition to the sensor fusion and machine learning algorithm (SVM) which are the...
This paper describes a new 120 fps (frames per second) real-time HEVC encoder for higher frame rate video encoding and transmission. Modification in the flexible customizable software architecture of encoder LSIs makes it possible to achieve the temporally scalable HEVC encoding with upward compatibility for existing 60 fps-based systems. The encoder also achieves 4K/120fps video encoding in real...
Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.
It is a pleasure for me to welcome you to the COOL Chips 20, the 20th anniversary of the IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies...
The following topics are dealt with: neurosynaptic integrated circuit; digital microfluidic biochips; supercomputer; flip-flops; ARM-FPGA; CPU; system-on-chips; vehicle intelligence; convolutional neural networks; silicon-on-insulator; STT-RAM; video signal processing; and CMOS integrated circuit.
The comparison our proposed model and the evaluation of a real accelerator chip appeared that the model is well matched to the real chip when the operational frequency is relatively low. Also, it appears that under the room light with a large inner resistance, the strong reverse bias is effective. With the bright light, a relatively weak reverse bias is advantageous. The improvement of the model for...
The comparison our proposed model and the evaluation of a real accelerator chip appeared that the model is well matched to the real chip when the operational frequency is relatively low. Also, it appears that under the room light with a large inner resistance, the strong reverse bias is effective. With the bright light, a relatively weak reverse bias is advantageous. The improvement of the model for...
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