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Verification is a critical step in the Integrated Circuit (IC) design process. In order to verify a design, a set of assertions based on the design, is generated. The design is checked, either using simulation or formal tools, to make sure that the design does not violate any of the generated assertions. If any of the assertions is violated, then a design bug is detected. The quality of the verification...
An effective optimization approach for the electromigration (EM) reliability in power grid (PG) has been presented in this paper. With core technology development and the key feature size of integrated circuits decreasing, it is more serious for the EM-induced failure occurrence in the entire PG. However, previous PG studies focus on supply noise optimization and neglect the EM influence in lines,...
This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing...
CMOS power dissipation has multiple components: switching, short-circuit, and static. In order to be robust to power attacks, digital logic should eliminate the relation between processed data and each and every power component. Other sources of side-channel information are glitches and the early evaluation of signals. We improve over our previous work and propose a Look-Up Table (LUT) with increased...
This paper proposes a layered decoder architecture for array QC-LDPC codes which targets tens of Gbps data rates. It relies on layer unrolling with pipeline stages in between layers, allowing simultaneous decoding of multiple layers. The most important features of the proposed decoder are: (i) fully parallel processing units within each layer (ii) hardwired layer interconnect that allows the removal...
A new high-performance VLSI architecture for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented. It is based on storing possible filter partial products in a look-up table (LUT) followed by a shiftaccumulation (SA) unit. Usually, all the address location of LUT need to be re-calculated in every iteration. In this paper, we proposed a new strategy for updating the...
A novel subthreshold sizing strategy utilizing the Inverse Narrow Width Effect is demonstrated that has the largest range of propagation delays within the same cell footprint and lowest variability of any subthreshold sizing strategy thus far proposed. Simulation results and ring oscillators implemented in a commercial 65nm low power process confirm a propagation delay improvement of up to 1.95X over...
In this paper, a low power 4-bit 400 MS/s standard cell based flash Analog-to-Digital Converter (ADC) is presented. The proposed flash ADC uses comparators based on the logic gates. Relationship between the input voltage and comparator reference voltage defines the output of comparator to be '1' or '0'. The comparator is followed by the gain booster and encoder. Low power consumption is achieved by...
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that...
This paper presents an asynchronous detector with priority encoding technique. Conventionally, a normal synchronous detector like an image sensor checks all the outputs of detection cells, whatever the cells are activated or not. Thus, it spends a lot of undesired power consumption. On the contrary, an asynchronous detector to only check the activated cells has a small power consumption, even though...
A systematic synthesis approach for designing a voltage-mode multifunction operational transconductance amplifier (OTA)-C biquadratic has been described using programmable first order filter. The proposed filter shows lower sensitivities, high frequency response, lower output noise. The proposed second order filter has been converted to third order butterworth and elliptic filter employing a single...
Caches have significant impact on an embedded system's performance and energy consumption. As a result, much prior research has focused on cache optimizations to minimize energy consumption and improve performance. Caches are also highly susceptible to side channel attacks, wherein an attacker analyzes leaked information from side channels to extract private information. A key challenge of security...
This paper proposed a 0.3 V, low power consumption, 24Ghz low noise amplifier (LNA), using 0.18 μm CMOS technology, and be widely used in frequency modulated continuous waveform (FMCW) radar. Base on three stages cascaded architecture and applying body bias technology in every stage to reduce power consumption significantly and keep gain and linearity. The proposed LNA gain and noise are 10.68dB and...
The current design drivers for multi-cores, namely performance per watt, scalability and flexibility, make the Networks-on-Chip (NoCs) the de-facto on-chip interconnect. State of the art NoCs can exploit heterogeneous solutions and complex DVFS techniques to fulfill also the variability of the application requirements. Relevant showstoppers to the design of a truly flexible NoC fitting all the possible...
This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL)...
Fault injection and fault simulation are a typical approach to analyze the effect of a fault on a hardware/software system. Often fault injection is done on abstract models of the system either to retrieve early results when no implementation is available, yet, or to speed-up the runtime intensive fault simulation on detailed models. The simulation results from the abstract model are typically inaccurate...
Neural network accelerators have been extensively studied for artificial intelligent applications for recent years. Analogto-information systems (AIS), which could accelerate neural network computation in analog domain, are considered as one better alternative for achieving higher scalability and energy efficiency. Unlike operating in the digital domain, an AIS adopts analog computing units to construct...
In this paper, we attempt a challenging task to unify two important complementary operations, i.e. contrast enhancement and denoising, that is required in most image processing applications. The proposed method is implemented using practical analog circuit configurations that can lead to near real-time processing capabilities useful to be integrated with vision sensors. Metrics used for performance...
Keeping track of body's vital signals is essential for a healthy life. Even if you are young and healthy it is crucial to monitor your vital parameters. A real time portable wearable device is proposed to increase the accuracy and minimize the power consumption that measures up to 5 signals during activity or rest times, with a mobile application to display and save the data. Moreover, the data is...
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