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Electron mobility of ultra thin body (UTB) GeOI «MOSFETs with body thickness (Tbody) down to 3 nm has been systematically investigated and significant mobility enhancement with decreasing Tbody has been observed for the first time. This channel thickness scaling induced mobility enhancement can be attributed to the unique physical property of ultra thin Ge where the electron effective mass reduces...
Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic...
We report the first demonstration of real-time monitoring of a single spin in a Quantum Dot (QD) using foundry-compatible Si MOS technology and a Split-Gate design with built-in charge detector. Since single-shot readout is an indispensable step in the pursuit of Si-based fault-tolerant quantum computing, this work contributes to asserting the fabrication of Si spin qubits in a MOS technology platform...
We have designed and fabricated a nonvolatile SRAM (NVSRAM) integrated with ferroelectric HfO2 capacitor, and experimentally demonstrated its nonvolatile functionality, for the first time. Sub-10nm-thick ferroelectric HfO2 capacitor shows excellent ferroelectricity and memory characteristics at low supply voltage. The NVSRAM with ferroelectric HfO2 capacitor is capable of storing and recalling previous...
A 3D ferroelectric Al doped HfO2 device for NAND applications was fabricated for the first time. The polysilicon (poly-Si) channel, whose diameter ranges from 60 to 200 nm, was highly doped for a better understanding of the ferroelectric properties. Electrical results confirmed the presence of the ferroelectric phase with a coercive voltage (2Vc) of 6 V extracted from the hysteresis loop. The drain...
We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SSrev) below kT/q over four decades...
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results...
An energy-efficient nonvolatile intelligent processor (NIP) is proposed for battery-less energy harvesting system. This NIP employs RRAM-based nonvolatile logics (NVL) with self-write-termination (SWT) scheme and low-power processing-in-memory (PIM) to achieve energy-efficient computing against frequent power-off situations. An NIP test chip was fabricated in 150nm CMOS process using HfO RRAM. This...
We report a circular-shape monolithic transistor-antenna (trantenna) for high-performance plasmonic terahertz (THz) detector. By designing an asymmetric transistor on a ring-type metal-gate structure, more enhanced (45 times) channel charge asymmetry has been obtained in comparison with a bar-type asymmetric transistor of our previous work. In addition, by exploiting ring-type transistor itself as...
Progressive impacts of aging on Fmax & noise margin of the precharge-evaluate domino read, and VMIN for differential static write & retention are demonstrated via statistical measurements over the operational lifetime of a 14KB 1R1W 8T SRAM array in 22nm high-k/metal-gate tri-gate CMOS.
This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive...
To optimize the classic design trade-off between EMI noise and power efficiency in GaN power drivers at 10MHz and beyond, a closed-loop adaptive Miller Plateau sensing (AMPS) technique is proposed. In order to mitigate long delays and low accuracy issues in conventional Miller Plateau (MP) sensing approaches, an emulated MP tracking (EMPT) technique is adopted to achieve instant MP start point sensing...
In this paper, we demonstrate for the first time an implant free In0.53Ga0.47As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating Vov of 0.6 V. In addition, an excellent electron mobility (μeff, peak=3531 cm2/V-s), low SSlin=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance,...
This paper demonstrates a cross point Cu based Resistive Random Access Memory (Cu-ReRAM) technology suitable for Storage Class Memory (SCM) applications. Two key technologies have been developed for large capacity of 100Gb-class SCM with 100 ns program speed and 10M cycles of program endurance. One is tight resistance distributions of Cu-ReRAM by inserting a barrier layer to prevent excess intermixing...
We present vertical InAs nanowire MOSFETs on Si with an In0.7Ga0.3As drain. The devices show Ion and gm/SS record performance for vertical MOSFETs and Ioff below 1 nA/μm at Vd 0.5 V. We show a device with gm=1.4 mS/μm and SS=85 mV/dec, therefore having Q-value (gm/SS) of 16. The device has Ion=330 μA/μm and 46 μA/μm at Ioff 100 nA/μm and 1 nA/μm, respectively. Furthermore, we show a device with SS=68...
One and two dimensional nanocarbon (NC) materials, including carbon nanotubes (CNTs), graphene and graphene nanoribbons (GNRs) have excellent properties and can therefore be building blocks of future electronic devices. It has been predicted and demonstrated that transistor channels and interconnects (More Moore devices) made of NC materials have excellent properties [1-6]. NC-based Beyond CMOS and...
Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing...
With TiN/ferroelectric-HfZrOx (HZO)/TiN capacitors as the platform, NH3 plasma treatment was employed at different HZO/TiN interfaces to investigate the impact on reliability. It has been electrically confirmed that HZO free from wake-up and fatigue effects up to 106 cycles (± 2.5 MV/cm, long pulses width of 1 ms) with high κ value of 29∼30, low leakage current and 2Pr of 20.2 μC/cm2 can be achieved...
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