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A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting...
This paper presents the first fully ultrasonic (US) high-precision implantable sensor with active US links for power-up, data downlink, and data uplink. The packaged implant measures just 1.7×2.6×8.1mm3 and includes a custom IC, piezoelectric devices (piezos) designed for data/power links, and a pressure transducer (PT). Characterization is performed at a large depth of 12 cm, in a phantom material,...
A VCO-based sensor readout circuit is presented. It comprises a VCO-based integrator with counters, and a capactively-coupled feedback DAC, to form a 1st-order DSM with high input impedance and wide dynamic range for voltage sensors. Chopping is applied to suppress the flicker noise. The time-domain approach relaxes the voltage swing requirement compared to that of a Gm-C integrator, and thus area...
A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.
This work presents an inductor-less 0.4 V cellular receiver (RX) front-end with an ultra-low power of 10 mW and an ultra-small area 0.31 mm2 in 16 nm FinFET technology, which enables massive receivers in a single chip for 10 Gb/s high throughput 5G system in sub-6 GHz band. The proposed inductor-less low-Vdd RX front-end consists of an LNA, passive mixers, LO generator and 20MHz bandwidth channel...
This paper presents a PLL-assisted crystal oscillator using a current switching phase detector (PD) with intrinsic 90° phase offset for IoT applications. The PLL provides accurate pulse injection timing into the XO, sustaining its oscillation at only 100mV amplitude and ensuring robustness operation across PVT. This technique achieves high energy injection efficiency and avoids the use of power hungry...
An FFE TX which automatically adapts impedance to arbitrary channel and RX impedances is proposed. Based on on-chip TDR monitoring, the TX impedance matching is adaptively relaxed without increasing reflection. In experiment, the proposed TX adapted to any combination of 35–75Ω channels and 30–200Ω RX impedances, achieving 3.8x eye improvement and the maximum data rate of 12Gb/s.
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power....
A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 4.2e-rms...
Waymo's self-driving cars contain a broad set of technologies that enable our cars to sense the vehicle surroundings, perceive and understand what is happening in the vehicle vicinity, and determine the safe and efficient actions that the vehicle should take. Many of these technologies are rooted in advanced semiconductor technologies, e.g. faster transistors that enable more compute or low noise...
Conventionally, SRAM PUFs are only used for chip ID. The proposed sequence dependent PUF expands the challenge-response space of an SRAM PUF by an order of rows(sequence length-1), making it suitable for authentication. In addition, it has a sequence dependent non-linear behavior making it more immune to machine learning attacks. In 28nm, the 64×64 SRAM-based PUF has a bit area of 388F2 with energy...
This paper proposes Recryptor, an energy efficient and compact ARM Cortex-M0 based reconfigurable cryptographic processor using in-memory computing. Recryptor is capable of accelerating a wide range of cryptography algorithms and standards, including public/private key cryptography and hash functions, by augmenting the memory of a commercial general purpose IoT processor resulting in a highly compact...
This paper presents a strong silicon physically unclonable function (PUF) immune to machine learning (ML) attacks. The PUF, termed the subthreshold current array (SCA) PUF, is composed of a pair of two-dimensional transistor arrays and a low-offset comparator. The fabricated PUF chip allows 265 challenge-response pairs (CRPs) and achieves high reliability with average bit error rate (BER) of 5.8%...
AI, Robotics, and loT are attracting wide attention, expected as technologies to change society in the future. These innovative technologies have potentials to build (1) a borderless communication society, (2) a symbiotic society between humans and robots, and (3) a safe and secure networked society. This paper describes some specific solutions by Panasonic: (1) automatic translation solution, (2)...
Embedded flash for low power sensing systems require very low write energy and peak power. This work proposes a 130nm, 1024×260 SONOS flash with an ultra-wide 1Kb program cycle, using efficient FN tunneling based programing and a dedicated, multi-output transition pump with charge sharing and charge recycling. Combined with energy efficient charge pumps, the proposed flash program energy is 122pJ/bit...
We propose computational-lock, a technique for accelerating frequency and phase-acquisition in all-digital PLLs during cold-start and re-lock. A wide-dynamic range, high resolution TDC is also proposed to further support the technique. Resulting lock-time improvements are evaluated through 50,000 repeated measurements of 65nm CMOS test-chips. Mean lock-times of 16Trefcik and 12Trefcik for cold-start...
This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160°C and data storage...
This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an adaptive bias voltage to compensate the saturated ID current caused non-linearity. The proposed LPDDR4 I/O is fabricated in 10 nm FinFET technology with...
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