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In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled...
We simulated the static behavior of scaled FinFETs employing a self-consistent Multi-Subband Ensemble Monte Carlo simulator for non-planar devices. To be able to take into account the three-dimensional device structure, the 2D Schrödinger equation is solved in several cross sections; the coupled solution of the 3D Poisson equation and the 1D Boltzmann transport equation through the ensemble Monte...
Recently, studies on ReRAMs and their reliability have received increased attention. The reliability issue is due to the nature of oxygen vacancies behaviour under biasing conditions which necessitate further studies to achieve an in-depth understanding. In this work, we fabricated several HfOx ReRAM devices with different structure, material, and thickness, followed by a study of their electrical...
This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs. We evaluate HexFET as a potential successor to FinFET for 5nm node logic and SRAM applications using first principles atomistic-based modeling, calibrated...
This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the efficiency of the SOT-MRAMs can be questioned in high-density memory application. To deal with this obstacle, we propose a multilevel cell which stores...
Cathode related current collapse effect in GaN on Si SBDs (Schottky Barrier Diode) is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-VDP (Van Der Pauw) are associated with temperature dependent dynamic Ron transients analysis showing that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation...
This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive...
A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET...
Amorphous InGaZnO (a-IGZO) is a candidate material for thin-film transistors (TFTs) owing to its large electron mobility. The development of high functionality circuits requires accurate and efficient circuit simulation that, in turn, is based on compact physical a-IGZO TFTs models. Here we propose a compact physical-based and analytical model of the drain current of a-IGZO TFTs. The model accounts...
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the...
The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and...
Single gate oxide defects in strongly scaled Tunneling Field-Effect Transistors with an inverse subthreshold slope well below 60 mV/decade are investigated by Random Telegraph Signal (RTS) noise measurements. The cause for RTS noise are electrons being captured in and released from individual defects in the gate oxide. Under the assumption that elastic tunneling is the underlying capture and emission...
This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations...
In this paper, we study the impact of different device architectures and material properties on the performance of two-dimensional tunnel FETs (2D TFETs). We show that single-gate (SG) device architecture in case of monolayer and few layers two-dimensional materials perform better than doublegate (DG) architecture. Due to sharper band bending at the tunneling junction, SG device offers shorter tunneling...
An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed.
SPlCE-compatible modeling with generalized lumped devices is used to simulate the spatial and time dependence of photogenerated carriers with standard circuit simulators. Equivalent voltages and currents are used in place of minority carrier excess concentrations and minority carrier currents respectively. The initial light-induced excess carrier concentration in silicon is accounted by means of distributed...
This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of...
We report on the thermal and electrical performance of nitrogen (N) and carbon (C) doped GeSe thin films for selector applications. Doping of GeSe successfully improved its thermal stability to 450°C. N doping led to a decrease in the off-state leakage and an increase in threshold voltage (Vth), while C doping led to an increase in leakage and reduced Vth. Hence, we show an effective method to tune...
Recently it was demonstrated that an asymmetric DRAM capacitor stack can introduce non-volatility and at the same time outperform ferroelectric HfO2 based FeRAM in terms of cycle endurance. With the present work, we provide an in-depth study of the underlying mechanisms and perform a comprehensive retention study that characterizes ferroelectric memories. Piezoelectric force microscopy is applied...
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