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Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation...
The performance of digital circuits can be improved by more efficient implementation. For certain circuits this can be done by using pass transistor logic. This paper compares pass transistor logic styles with the standard CMOS logic style. It will be shown that pass transistor logic is able to outperform the standard approach, not only by simulation but by measurements in silicon. Measurements have...
An integrated receiver chip for external photodiodes (PDs) is presented in 0.6µm BiCMOS technology with 3.3V supply voltage. It consists of an internal Automatic Gain Control (AGC), which simultaneously compensates the frequency characteristics, an internal charge pump, which delivers optionally 5V to external PDs, a detector to show whether data is received and a 50Ω differential...
In this paper, we propose a novel mixed-signal cancellation circuit for LTE carrier aggregation receivers targeting modulated spur interference. This circuit senses interference via an auxiliary analog path, and generates a reference signal for the adaptive digital cancellation. To evaluate the performance of the proposed technique, a demonstrator, realized in 28 nm LP CMOS, is shown with a cancellation...
We present a set of tools for digital design, integration and verification of mixed-signal Application Specific Integrated Circuits (ASIC) developed within our design team. We have chosen Python for the development of the tools. By drawing on Python's features we have developed tools targeting many steps required across a design flow: a) Complex digital blocks are auto-generated, where Python generates,...
This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary...
A compact inductorless E-band static frequency divider with the division ratio of 8 is reported in this paper. It has a sensitivity of -43 dBm at the self-oscillating frequency of 75.3 GHz and sports the sensitivity better than -14 dBm in a frequency range from 70 to 77 GHz. The divider consists of 3 emitter-coupled logic based dividers with the division ratio of 2. High frequency of operation and...
The understanding and controlling of semiconductor process variation is crucial to the performance, functionality and reliability of modern ICs. Due to the complex fabrication process involving hundreds of processing steps, the analysis of the sources of variability is a non-trivial task. In this paper, a novel, simple-to-implement procedure named Hierarchical Median Polish is proposed. The method...
This paper reviews trends for ultra-low-power wireless transceiver system and integrated circuit design under the perspective of using cost-effective CMOS technology nodes. These efficient transceiver structures typically find application in devices such as fitness monitors and other wearable healthcare devices, Internet of Things (IoT) devices and generic sensor nodes. A brief overview of State-of-the-Art...
This work presents a demonstrator for safety-critical applications based on a low-cost FPGA platform. The main goal of the demonstrator is to show the features and benefits of a fault-injection tool for FPGAs called FIJI (Fault Injection Instrumenter) that was developed by the authors of this paper. Besides, the demonstrator should illustrate typical sources of hardware/software faults as well as...
In this work, the implementation of the chargecontrolled method in a CMOS chip is presented. The idea of the method is that the transferred total charge quantity is composed of a number of packets which are intended to stimulate the cells of the retina electrically. In addition, it will be compared with already established methods. The influence of electrode interfaces on the process is investigated...
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