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In a closely coupled heterogeneous computing system the work is shared amongst all available computing resources. One challenge is to find an optimal division of work between the two or more very different kinds of processing units, each with their own optimal settings. We show that through the use of statistical techniques, a systematic search of the parameter space can be conducted. These techniques...
Current handhelds incorporate a variety of acceler-ators/IPs for improving their performance and energy efficiency. While these IPs are extremely useful for accelerating parts of a computation, the CPU still expends a significant amount of time and energy in the overall execution. Coarse grain customized hardware of Android APIs and methods, though widely useful, is also not an option due to the high...
Datacenters provide flexibility and high performance for users and cost efficiency for operators. However, the high computational demands of big data and analytics technologies such as MapReduce, a dominant programming model and framework for big data analytics, mean that even small changes in the efficiency of execution in the data center can have a large effect on user cost and operational cost...
All new Microsoft Azure and Bing servers are being deployed with an FPGA that sits both between the server and the data center network and on the PCIe bus. The FPGA is currently being used to accelerate networking on Azure machines and search on Bing machines, but could very quickly and easily be retargeted to other uses as needed. In this talk, I will describe how we decided on this architecture,...
Modern high-performance electronics are embedded in smartphones, self-driving automobiles, and augmented reality wearable. These computing platforms are high performance and multifunctional. One of the major performance limiting factors in these platforms is the poorly designed thermal solution that is triggered to prevent overheating at the processor transistor junction and at the platform surface...
Modern multi-core systems employ shared memory architecture, entailing problems related to the main memory such as row-buffer conflicts, time-varying hot-spots across memory channels, and superfluous switches between reads and writes originating from different cores. There have been proposals to solve these problems by partitioning main memory across banks and/or channels such that a DRAM bank is...
Designing and optimizing computer systems require deep understanding of the underlying system. Historically many important observations that led to the development of essential hardware and software optimizations were driven by empirical studies of program behavior. In this paper we report an interesting property of dynamic program execution by viewing it as a changing (or social) network. In a program...
He VMware ESXi hypervisor attracts a wide range of customers and is deployed in domains ranging from desktop computing to server computing. While the software systems are increasingly moving towards consolidation, hardware has already transitioned into multi-socket Non-Uniform Memory Access (NUMA)-based systems. The marriage of increasing consolidation and the multi-socket based systems warrants low-overhead,...
Datacenters often are a power utility's largest consumers, and are expected to participate in several power management scenarios with diverse characteristics in which Energy Storage Devices (ESDs) are expected to play important roles. Different ESD technologies exist, including little explored technologies such as flow batteries, that offer different performance characteristics in cost, size, and...
The advance of next-generation sequencing (NGS) technology has dramatically reduced the cost of genome sequencing, which is a key technology to enable precision medicine. However, processing and analyzing the huge amount of data collected from NGS sequencers introduces significant computation challenges, and has become the bottleneck in many research and clinical applications. This has become a major...
Energy-use is a key concern when migrating current deep learning applications onto low power heterogeneous devices such as a mobile device. This is because deep neural networks are typically designed and trained on high-end GPUs or servers and require additional processing steps to deploy them on low power devices. Such steps include the use of compression techniques to scale down the network size...
Modern computer systems are accelerator-rich, equipped with many types of hardware accelerators to speed up computation. For example, graphics processing units (GPUs) are a type of accelerators that are widely employed to accelerate parallel workloads. In order to well utilize different accelerators to gain better execution time speedup or reduce total energy consumption, many scheduling algorithms...
Programming Micron's Automata Processor (AP) requires expertise in both automata theory and the AP architecture, as programmers have to manually manipulate state transition elements (STEs) and their transitions with a low-level Automata Network Markup Language (ANML). When the required STEs of an application exceed the hardware capacity, multiple reconfigurations are needed. However, most previous...
Cameras are the defacto sensor. The growing demand for real-time and low-power computer vision, coupled with trends towards high-efficiency heterogeneous systems, has given rise to a wide range of image processing acceleration techniques at the camera node and in the cloud. In this paper, we characterize two novel camera systems that use acceleration techniques to push the extremes of energy and performance...
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