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In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by...
A novel and simple structure for improving CMRR is introduced. This structure can be added to the circuits like folded cascode amplifier, telescopic amplifier, current buffers, .etc to improve the CMRR of these circuits. This simple and effective circuit uses common mode deviating technique to improve CMRR at least 12dB while preserves CMRR bandwidth which is a novel technique in order to improve...
This work demonstrates a new integrated inverse class E amplifier circuit, employing a pHEMT switching device and fully integrated output network for pulse shaping. The circuit is particularly suitable for full integration, since it does not need any RF choke for biasing, and no DC blocking capacitor is needed between the switch and the output network parallel resonance circuit. The back plate capacitances...
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and...
Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to...
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling...
This paper presents an implemented 4-bit phase ADC circuit. It introduces a model to calculate its dynamic range considering second order effects including non-linearity and offsets. The study also encompasses the phase resolution and validates the model with measurement results from the implemented chip. Our analysis shows that the phase ADC is extremely robust against circuit non-idealities and...
Minimizing power consumption without compromising speed in any integrated circuit (IC) is a challenge. Employing multiple supply voltages (multi-Vdd) is an effective technique to achieve this. In order to minimize the power dissipation in an integrated circuit, voltage level converter circuits are required. There are two novel multi-threshold voltage (multi-Vth) based level converters are proposed...
This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation...
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
This paper demonstrates how micromechanical on-chip MEMS resonators can be used as higher-order mixer-filters in RF front-end WSN nodes. Vibrating FFSFRs (Free-free Square Frame Resonator) connected together can create 4th and 6th order mixer-filter responses. The output is further enhanced by an on-chip amplifier, thus reducing stray capacitances. These mixer-filters are fabricated utilizing a CMOS-MEMS...
The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency...
SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively...
A digital process, voltage, and temperature (PVT) calibration loop for a Frequency-to-Voltage converter (FVC) is presented. The FVC needs a precisely controlled delay element, but delay in CMOS is highly dependent on the PVT condition making it necessary to calibrate the delay line. The system is designed to calibrate against an external reference frequency which is already present in the intended...
This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole...
A DC-invariant gain control technique is introduced for differential CMOS variable-gain low-noise amplifiers (VG-LNA). Such technique provides an advantage of invariant DC bias current when the RF power gain is tuned over the gain control range. Therefore, the transconductance of NMOS transistor is unchanged, which minimizes the input match detuning. Consequently, the optimal design for noise, gain...
The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable...
The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is...
This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally,...
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