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A 1-inch optical format, 14.2M-pixel, 80fps, digital-output CMOS image sensor that employs a row-shared dual conversion gain pixel is presented. To achieve the 80 fps readout rate, a pipelined pixel reset/readout scheme named “nesting scan” has been introduced, where the charge sense node inside a pixel is reset during the previous row. Readout noise and maximum handling signal charge of the sensor...
A 2D/3D image sensor with reconfigurable pixel array and column-level background suppression scheme is presented for high resolution outdoor imaging. The proposed pixel array employs pixel binning and superresolution techniques for adaptable resolution. The sensor achieved a 5.9µm pixel and was able to capture full resolution outdoor depth images under daylight over 100klx.
We developed an ultra-low noise image sensor in which an organic photoconductive film (OPF) is laminated on the entire surface of the pixel circuits. In order to suppress the kTC noise in the pixel circuit of a three transistor configuration, a high-speed column feedback noise cancel circuit is newly developed. An ultra-low noise of 2.9 electrons during the horizontal blanking period of only 5 µs...
A wide-field fluorescence lifetime imager capable of up to 100 frames per second (fps) is presented. The imager consists of a 64-by-64 array of low-noise single photon avalanche diodes (SPADs) in a standard 0.13-µm CMOS process, 4096 time-to-digital converters, and an application specific data path to enable continuous image acquisition at a total output data rate of 42 Gbps. These features combine...
An 820-GHz 8×8 imaging array using diode-connected NMOS transistor detectors is demonstrated in 130-nm CMOS process. Measured mean responsivity of 3.4 kV/W and mean NEP of 28 pW/Hz1/2 at 1MHz modulation frequency are achieved. The NEP is 3.5X lower than that of NMOS and slightly lower than that of Schottky diode terahertz imaging arrays implemented in CMOS. The minimum NEP is 15.5 pW/Hz1/2, which...
A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on another silicon interposer chip in 65nm technology. Total 1024 DQ bus operating in 1.1Gbit/s with Vmin=0.3V are proven in experimental results. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY...
A 3D IC heterogeneous chip integration of 65nm RF receiver, 28nm baseband processor, and 40nm DRAM on a proprietary CoWoS structure is demonstrated and its electrical characterization of KGS (Known Good Stack) has revealed a highly comparable system performance as compared to that of the KGD (Known Good Die) testing data. Moreover, an innovative system BIST (Built-in-Self-Test) scheme and methodology...
This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer...
3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions,...
A “scalable 3D-FPGA” using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Moreover,...
A 6-port, 2-lane packet-switched input-buffered wormhole router forms the key building block of a 2×2 2D mesh network-on-chip (NoC). The router operates across a wide frequency (voltage) range of 1GHz (0.85V) to 67MHz (340mV), dissipating 28.5mW to 675µW and achieves 3.3X improvement in energy-efficiency at an optimum supply voltage (VOPT) of 400mV. The resilient router incorporates an end-to-end...
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency...
We have realized the characterization of MOSFET noise up to 3 GHz by locating a low-noise (LN) transimpedance amplifier (TIA) close to the devices to be tested (DUTs). A noise floor as low as 3 pA/vHz was achieved by using an external high-voltage input. Moreover, a high-frequency noise probe equipped with a TIA IC was fabricated, with which measurements in a frequency range up to 800 MHz were achieved...
This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to...
Physiological study requires simultaneous electrical and chemical recording at the synaptic level with high-density (HD) micro-electrode arrays (MEA). This paper presents a 200-channel IC for HD-MEA dual-mode signal acquisition. With the large amount of channels, both current and voltage channels are designed with minimal power and area while achieving low noise and good linearity. To minimize the...
This paper describes a system-on-chip (SoC) fabricated in 0.35µm 2P/4M CMOS for high-fidelity neurochemical pattern generation in vivo. The SoC uniquely integrates electrical stimulation with embedded timing management and 400V/s fast-scan cyclic voltammetry (FSCV) sensing, and manages a novel switched-electrode scheme that eliminates the possibility of large stimulus artifacts adversely affecting...
An energy-efficient epileptic seizure detection system-on-chip (SoC) is integrated in 10.41mm2 in 0.18µm CMOS. The chip integrates analog frontend, a 16-bit ADC, a 32-bit processor, hardware accelerators, and data control unit (DCU) for epileptic signal processing. A 32.8x processing time reduction and an 8.5x energy reduction are achieved through hardware-software co-design. The chip dissipates 28...
We report on a CMOS microelectrode array system chip for recording and stimulation of electrogenic cell cultures and tissues, featuring a sensing area of 8.09 mm2, composed of 26'400 electrodes at 17.5 µm pitch. A user-configurable selection of the electrodes can be routed to 32 stimulation units and to 1024 recording channels with 2.4 µVrms input-referred noise and 10-bit 20-kS/s A/D conversion....
This paper presents the design of a low-power highly sensitive impedance analyzer for electrochemical impedance spectroscopy (EIS) in a 0.18µm CMOS process. The analyzer uses a low-power current buffer with high gain to suppress the noise from the back-end. A heterodyne mixer is designed to reduce the flicker noise of following stages. It also enables the simultaneous recording of the amplitude and...
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