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Humanity is currently faced by an immense task. The world's population will continue to grow in the coming decades, especially in emerging nations. The living conditions of billions of people can only be improved and their prosperity increased if sufficient energy is available. The desire for mobility will accompany this growth and create even higher energy needs. What are the solutions to these challenges,...
It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product - 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their significantly improved electrostatics. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant...
Micro-Electro-Mechanical Systems (MEMS) are sensing the environmental conditions and give input to electronic control systems. MEMS are miniature systems which usually combine tiny mechanical structures with electronic circuits. Typical MEMS structures have a size of a few micrometers. MEMS sensors make system reactions to human needs more intelligent, precise, and at much faster reaction rates than...
As the computation and communication circuits we build radically miniaturize (i.e. become so low power that 1 pJ is sufficient to bang out a bit of information over a wireless transceiver; become so small that 500 µm2 of thinned CMOS can hold a reasonable sensor front-end and digital engine), the barrier to introducing all sorts of interfaces and control loops into organisms will lower radically....
Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling...
Compressive sensing (CS) [1]–[3] has emerged in the last decade as a powerful tool and paradigm for acquiring signals of interest from fewer measurements than was thought possible. CS capitalizes on the the fact that many real-world signals inherently have far fewer degrees of freedom than the signal size might indicate. For instance, a signal with a sparse spectrum depends upon fewer degrees of freedom...
Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital resources to enhance performance-limiting analog building blocks has become a widely explored paradigm in modern ICs. This paper reviews the state-of-the-art in digitally assisted data converter design and provides an overview of commonly used techniques.
Analog circuits perform critical operations in any modern integrated circuit. Digital integrated circuits require analog circuits for logic or I/O clock generation, as well as for temperature monitoring or supply regulation. In mixed signal products, analog circuits perform the critical translation of information from the physical (analog) world to the digital world of ones and zeros. Analog-to-digital...
Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ∼2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing...
A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed...
We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-µm CMOS technology can...
We propose a supply noise rejection technique, which is applied to an all-digital phase-locked loop (ADPLL). Supply noise is cancelled by adding a cancellation current whose fluctuation is the same as that of a supply-noise component in an oscillator current. The proposed technique is realized with a small area and current dissipation, and is tolerant to process, voltage, and temperature (PVT) variations...
A 65 nm CMOS LO generation system capable of providing quadrature signals over the wide 2 to 16GHz frequency range for short-range radar applications is presented. Made of a 6.5 to 18.4GHz PLL, and an injection-locked programmable divider by 1, 2, or 4, it features a phase noise at 10MHz offset < −129 dBc/Hz, a RMS jitter < 0.68 ps, a reference spur level < −48 dBc, and a settling time of...
Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing...
In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to...
In this paper, a video rendering ASIC for multiview automultiscopic displays using an image domain warping approach is presented. The video rendering core is able to synthesize up to nine interleaved views from full-HD (1080p) stereoscopic 3D input footage. The design employs elliptical weighted average (EWA) splatting to perform the image resampling. We use the mathematical properties of the Gaussian...
This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning. The chip was used as part of a ADC/DSP/DAC chain which, unlike the case with conventional, clocked systems,...
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