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Model-based Systems Engineering plays a key role in the automotive industry by reducing the development costs while designing more complex controllers. Thanks to the continuous improvement of models accuracy and their computational performance, introducing system simulation in form of “in-the-loop” simulations in early stages of the development is possible. However, this is often limited by the efforts...
In a modern chip development cycle non-mainline / non-functional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of non-mainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and...
Many computer systems employ dynamic power management (DPM) to maximize power efficiency. DPM offers great opportunities, but deploying it carries significant risks if the DPM scheme is not completely verified. We propose architecting the DPM scheme such that it can be formally verified regardless of the size of the system.
FPGA devices provide a range of security features which can provide powerful security capabilities. This paper describes many security features included in present-day FPGAs including bitstream authenticated encryption, configuration scrubbing, voltage and temperature sensors and JTAG-intercept. The paper explains the role of these features in providing security capabilities such as privacy, anti-tamper...
This paper describes how a stealthy Trojan circuit can be inserted into a stream cipher module. The stream cipher utilizes several shift register-like structures to implement the keystream generator and to process the encrypted text. We demonstrate how an effective trigger can be built with the addition of just a few logic gates inserted between the shift registers and one additional flip-flop. By...
ISO 26262 is the new standard for automotive functional safety. This standard identifies major process steps across a large number of system stages as well as safety-related artifacts required as input and output of these steps. The VeriSpec project intends to identify the main challenges for the adoption of ISO 26262 by the heavy-vehicle industry and to provide useful and industrially relevant “components”...
Recent advances in hardware security have led to the development of FANCI (Functional Analysis for Nearly-Unused Circuit Identification), an analysis algorithm that identifies stealthy, malicious circuits within hardware designs that can perform backdoor operations to compromise security. Evaluations of such methods using benchmarks and academically known attacks are not always equivalent to the dynamic...
The necessity of detecting malicious modifications in hardware designs has led to the development of various detection tools. Trojan detection approaches aim to reveal compromised designs using several methods such as static code analysis, side-channel dynamic signal analysis, design for testing, verification, and monitoring architectures etc. This paper demonstrates new approaches for circumventing...
In SoC, key infrastructure/backbone flows are distributed across many IPs and involve tight firmware and hardware interaction. Examples include resets, power management, security, and more. Traditional hardware validation techniques are no-longer adequate for such flows, due to the short time-to-market requirements, in particular, for mobile devices. In this paper, we articulate the challenges and...
To address the concern that a complete detection scheme for effective hardware Trojan identification is lacking, we have designed an RTL security metric in order to evaluate the quality of IP cores (with the same or similar functionality) and counter Trojan attacks at the pre-fabrication stages of the IP design flow. The proposed security metric is constructed on top of two criteria, from which a...
In this paper, we firstly give an overview of the security perimeter in modern automotive systems and propose then a cost effective solution for authentication of communication data. The proposed solution provides end to end protection, it covers the aspects data content and generation time (freshness) and it can be implemented for different standard communication busses without a bus protocol change...
Circuit camouflage technologies can be integrated into standard logic cell developments using traditional CAD tools. Camouflaged logic cells are integrated into a typical design flow using standard front end and back end models. Camouflaged logic cells obfuscate a circuit's function by introducing subtle cell design changes at the GDS level. The logic function of a camouflaged logic cell is extremely...
In this paper, we presented our recent characterization and analysis on the power consumption of smartphone radio components, including Wi-Fi, GPS and cellular (3G/4G) modules. Different from previous research that focused on the properties of single module under a limited number of usage scenarios, our works are performed on the statistically selected representative Apps with four generations of...
The rising size and complexity of in-car networks call for more advanced and scalable verification solutions. We propose a verification methodology for in-car networks based on a system level test generator tool used for creating massive random biased stimuli, and on coverage and checking monitors. The test generator is an expert system based on an ontology of testing knowledge. A significant challenge...
We propose a novel cache set index scheme called SWAP (swap-based cache set index). SWAP introduces a pseudo-physical address space that is used by the operating system. The real physical address used for cache and main memory access is obtained by simply swapping some of superpage number bits with cache set index bits from the pseudo-physical address. By adding a level of indirection to the physical...
Cell-to-cell variability of batteries is a well-known problem especially when it comes to assembling large battery packs. Different battery cells exhibit substantial variability among them due to manufacturing tolerances, which should be carefully assessed and managed. Although battery packs usually incorporate some cell balancing circuitry, it is supposed to balance cell voltages dynamically at the...
Conventional, pre-RTL SoC architectural design space exploration does not account for the chip's floorplan. However, the power and performance of integrated CPU-GPUs are highly dependent not only on architectural specifications and workload characteristics but also on the underlying floorplan. We develop a floorplan-aware system-level analysis framework for integrated CPU-GPUs and demonstrate that...
The Hybrid Memory Cube (HMC) is a 3D-stacked DRAM architecture designed for substantially improved memory bandwidth. In particular, its I/O interface achieves up to 320GB/s of external bandwidth through high-speed serial links. However, it comes at a cost of large static power of off-chip links, which dominates total power consumption of HMCs. Therefore, we propose an adaptive mechanism to partially...
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