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A high yield copper damascene process requires defect-free copper surfaces after Cu CMP. In this paper we present a novel technique to improve cleaning efficiency, especially the removal of particles in the range of 20 to 80nm. This innovative Chemical Mechanical Cleaning (CMC) approach is validated with defect density reduction and a significant reduction of electrical shorts measured on test wafers.
The NVD inspection system detected radial “streak” like NVDs at the post Cu CMP clean process that were not detected by the optical inspection system. Layer to layer overlay of the NVD defect maps from the current Cu CMP layer with the optical defect maps from post nitride deposition and the next copper interconnect level revealed that the NVDs were truly the root cause of the yield critical defect...
The objective of this paper is to elucidate novel applications where the low frequency component of a background signal (haze) level of a wafer inspection tool can be used to qualitatively analyze different epitaxial processes. During initial epitaxial development cycles, a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the wafer, a semi-quantitative way...
This paper describes the methodology, results and improvements for defect reduction in the Front End of Line of a 20nm planar technology. The defect inspection optimization and defect reduction methodology described were implemented for the High-k Metal Gate (HKMG) stack module on 300mm wafers for high performance logic devices.
With the continuous shrink of technology nodes, lithography becomes more and more challenging. At 20 nm node, double patterning technology (DPT) was the usual way of achieving the fine device structures. Until EUV is available as a high volume manufacturing (HVM) solution, DPT or triple patterning technology (TPT) will be required to sustain scaling. However, as the industry goes forward with scaling,...
This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail - sensitivity to time, design...
In this paper, production of lots under time constraints in a semiconductor wafer fabrication is investigated. A time constraint covers a sequence of process steps and has a maximum time that lots must spend in these steps. Lots which violate a recommended time constraint have to be scrapped or reprocessed. Accordingly, controlling the entrance of lots in a time constraint is critical in semiconductor...
Cycle time requirements from prime or major customers contradict the ever-increasing complexity of wafer fabrication. Lot size variations show up as significant cycle time improvement potential for single wafer processes. Further reduction potential aside of process times is shown regarding tool-internal waiting times. A model is elaborated to assure cost efficiency while significantly reducing lot...
Infineon Technologies Dresden establishes the worldwide first highly automated high volume production for power semiconductors based on 300 mm thin wafer technologies. For this special manufacturing platform, there are a lot of challenges for manufacturing and automation. During the research phases in preparation for the future 300 mm pilot lines different simulation studies for wafers, substrates...
Advanced process control (APC) is widely used in semiconductor manufacturing to adjust process parameters, ensuring a high product quality, while WIP flow optimization systems for scheduling & dispatching make decisions by assigning lots to tools for processing. APC imposes additional constraints to the operational decisions. It is critical to understand the relationship between these two aspects...
In this paper, the observation of active area line collapse in 20 nm planar NAND Flash technology is reported. The mechanism of active area pattern collapse is described using the theory of capillary forces. The proposed model for pattern collapse is validated by data obtained by real time defect analysis and end of line electrical data. Next, with the help of an empirical model, key structural metrics...
Stand-alone Electrically Erasable Programmable ROM (EEPROM) are widely used in industrial, automotive and portable consumer applications. Requirements for high density EEPROM have been steadily increasing in recent years. As deep submicron nodes are used to achieve highly dense bit-cells, the propensity for process-induced defects associated with compact isolation rules and architecture also increase...
This paper presents a case study on a process excursion where a subtle defect spray with twelve pairs of defects aggregated flow pattern on the front side of the wafer. The defect of interest is molten tungsten (W) balls which are generated in a dielectric etch chamber caused by plasma arcing between one part of the etch chamber and the dissimilar W film remaining on the wafer bevel. Observations...
In advanced technologies as the dimensions shrink, even the slight change in profiles can cause issues in BEOL integration. This paper discusses the effect of dielectric profile on product yield. Even though these issues were not seen on standard monitoring structures, the issue has been observed in products of very complicated design structures. The yield losses for this failure mechanism range from...
Shrinking process windows for advanced processing of complex devices, sub-14nm, require advanced topography control. Within-wafer topography variations impact the uniformity of subsequent layers and can affect yield. Process tools can generally control global uniformity across wafer, but are not well equipped to fine-tune the local (reticle-to-reticle) topography. Advanced new process tools such as...
A novel “adaptive pattern registration” method is developed which gives a reliable estimate of various film thickness in a wafer level TSV. The film thickness are measured using picosecond ultrasonic metrology technique. The adaptive pattern registration method provides higher measurement accuracy at reduced cycle time in comparison to Scanning White-Light Interferometry based technique. It will be...
Optical profilometer measurements are contact-free and fast. The depth of single high-aspect-ratio trenches and the step height of opaque materials can be measured. Deep trenches (50–225 µm) are measured with a white light interferometer. Shallower trenches and step height profiles are measured with a chromatic white light sensor. A vertical resolution of 6 nm and a lateral resolution of 2 µm make...
In this paper, we present an integrated in-line solution, combining automatic visual inspection/classification with unique 2D/3D measurement technologies, which was used to characterize the defectivity and the morphology of open through silicon via (TSV) structures. The measurements were performed on 300mm Si wafers hosting several populations of via with diameter varied from 5 to 20 micron, and target...
Like the 300mm standards, the 450mm physical interface standards define the multitude of parameters that are essential to factory automation and interoperability. In addition, 450mm standards drive factory efficiency much farther than the 300mm standards did. This paper will review the standards architecture and critical parameters defined by the standards with a focus on the efficiency improvements...
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