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It is our great pleasure to welcome you to the 2015 ACM/IEEE International Symposium on Low Power Electronics and Design - ISLPED'15, in the “eternal city” of Rome, Italy. This year's symposium continues its two decade long tradition of being the premier forum for presentation of research results and industrial experience reports on leading-edge issues in low power design. ISLPED has always been unique...
Computing platforms operating at the limits of energy-efficiency need to contend with the issue of robustness. This energy vs. robustness trade-off is fundamental in such systems. This talk will describe a Shannon-inspired framework referred to as statistical information processing (SIP). SIP navigates the energy vs. robustness trade-off by treating the problem of energy-efficient computing as one...
In an era in which foundry technologies are a commodity, product differentiation comes by design. As fabless becomes mainstream, a paradigm shift demands innovation and collaboration among industrial and research thinking to further lower the cost of ICs, as well as to address upcoming power-performance challenges. High performance mixed signal (HPMS) platforms require stringent overall system and...
On behalf of the Organizing Committee, it is our pleasure to welcome you to the 20th IEEE/ACM International Symposium on Low Power Electronics and Design, 2015, (ISLPED'15), held in Rome, Italy, on July 22–24, 2015. 20 years ago, a group of visionaries noted the avid interest in low-power design in many different disciplines and recognized the need to bring these diverse groups together with the goal...
Technology advances are creating major shifts in the industrial landscape. Traditional sectors such as transportation, medical and avionics, are witnessing fundamental changes in the supply chain and in the content where the interactions between the physical world and the computing world are becoming increasingly tight. Cyber Physical Systems, Systems of Systems, Internet of Things, Industrie 4.0,...
We present a novel technique for optimizing the read operation of spin-transfer torque (STT) MRAMs by employing a correlated material in conjunction with a magnetic tunnel junction (MTJ). The design of the proposed memory cell is based on exploiting the orders-of-magnitude difference in the resistance of the two phases of the correlated material (CM) and triggering operation-driven phase transitions...
Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection...
The emerging resistive random-access-memory (RRAM) crossbar provides an intrinsic fabric for matrix-vector multiplication, which can be leveraged as power efficient linear embedding hardware for data analytics such as compressive sensing. As the matrix elements are represented by resistance of RRAM cells, it imposes constraints for the embedding matrix due to limited RRAM programming resolution. A...
Phase-change memory (PCM) has gained much attention recently since it offers several advantages over DRAM, such as high cell density and low leakage power. PCM has similar read power and latency as DRAM; however, its write power and latency are significantly higher than DRAM. Therefore, one challenge with PCM is how to increase write throughput under write power budget constraints. To increase write...
Modern SoCs are characterized by increasing power density and consequently increasing temperature, that directly impacts performances, reliability and cost of a device through its packaging. Thermal issues need to be predicted and mitigated as early as possible in the design flow, when the optimization opportunities are the highest. In this paper, we present an efficient framework for the design of...
A thermoelectric (TE) device can be used as a heat pump that consumes electric power to cool a processor chip, or it can be used as a heat engine that generates electricity from the heat dissipated during processor operation. To better understand the use of TE devices, we develop a fully instrumented processor-based system with controllable TE devices. We first examine the use of TE devices for energy...
CMOS scaling trends lead to elevated on-chip temperatures, which substantially limit the performance of today's processors. To improve thermal efficiency, Phase Change Materials (PCMs) have recently been used as passive cooling solutions. PCMs store large amount of heat at near-constant temperature during phase change, allowing strategies such as computational sprinting. While existing sprinting methods...
This paper, for the first time, experimentally demonstrated the in-package microfluidic cooling on a commercial System-on-Chip (SoC). The pinfin interposer attached to the commercial SoC achieved energy efficient cooling for the SPLASH-2 benchmark suite in measurement. The low-power piezoelectric pump controlled by the SoC ensures the thermal integrity and reduces the system-level energy consumption...
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