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Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
Manually designing analog circuits is often considered as a difficult task that takes a lot of time. If a design automation environment is available for analog circuits, it is useful for designers to cope with the increasing challenges in advance process. In this paper, a reliability-aware circuit sizing technique is proposed to consider process variation, circuit aging, and layout-dependent effects...
Building the behavioral model for each circuit block is an efficient approach for mixed-signal system verification. If an automatic model generator is available to extract the required behavioral model from the given circuit netlist, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, this paper proposes a divide...
As a process technology is scaling, a reliability problem that may cause a failure in the functionality of the digital circuit becomes an important issue in System-on-Chip (SoC) design. This importance leads to the studies on fault diagnosis and tolerance. In this paper, we propose a static and analytical technique for fault diagnosis focused on the digital circuit. Gate level fault analysis is completed...
In this paper we have proposed a way of a model-based CMP proximity correction in sub-28nm SoC (system-on-a-chip) designs. Just like OPC (optical proximity correction) process against lithography variations, the proposed approach can be added at the mask synthesis stage in addition to the conventional metal fill approach and highly reduces the systematic process variation due to CMP.
Internet of Things represents a challenge in the automotive industry development, as it demands for innovation, integration, safety and security. These lead to highly sophisticated requirements set for the design process. The difficulty of managing natural language requirements may lead to inherent errors such as incompleteness, ambiguousness, etc. Adding formality to the requirements is recognized...
GPU (Graphics Processing Unit) is emerging as a key 3D/2D graphics and parallel workload accelerator in various SoC applications. As semiconductor fabrication technology continues to scale, chips (especially those with extremely high transistor counts such as processors) are becoming increasingly vulnerable to faults that could produce unwanted errors in computing. The most severe problem is Silent...
A future smart phone will become a mobile terminal that communicates with a number of diverse sensors perpetually. This never-resting RF communication will cut the battery life drastically, unless the power consumption per RF communication reduces accordingly while maintaining reasonable performance. This paper presents the recent evolution of a translational circuit (or N-path filter) to enable a...
A low-voltage phase-locked loop (PLL) circuit having a charge pump (CP) with a novel negative feedback replica bias scheme for current mismatch compensation is demonstrated. A prototype 400-MHz PLL circuit operating at 0.65-V is fabricated with 180-nm standard CMOS process. Measurement results show that current mismatch compensation is successfully achieved. Our PLL consumes only 140-μW.
This paper presents a 10 Gbps serializer/deserializer (SerDes) with a phase interpolator (PI) based clock and data recovery (CDR) circuit for high-speed and short-range wireless chip-to-chip communication. The SerDes performs 4:1 muxing and 1:4 demuxing functions. The PI-based CDR uses an 8-phase delay-locked loop (DLL) to produce a set of evenly spaced reference clock phases. The phase vernier, then...
A low phase noise META-VCO applying meta-structure was designed using 65nm CMOS process. The META-VCO operates 8.45∼8.77 GHz according to VCTRL, and the output power is −19.12 dBm. The measured phase noises are −67.8 dBc/Hz, −96.37 dBc/Hz, and −107.37 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz respectively. The power consumption is 28 mW with 1.2-V supply voltage.
This paper introduces a direct conversion transmitter for IEEE 802.15.4 applications with a high gain up-conversion mixer. An RF DCT (Direct Conversion Transmitter) is composed of differential-ended DAC (Digital to Analog Converter), passive low pass filter, quadrature active mixer, and drive amplifier. The most important thing in designing RF direct conversion transmitter is satisfying 2.4GHz Zigbee...
A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD's locking range is wider than the VCO's tuning range, which ensures the PLL can safely lock across the VCO's full tuning range. Also, a tuned buffer with a...
A distributed energy detection scheme that exploits the spatial-temporal correlation is proposed for heterogeneous cognitive radio (CR) sensor network. We first use the weighted centroid algorithm to localize the position of the PU. Then according to the localization result, selective measurement combining for weighted average consensus is adopted to fuse the energy detection outputs of only homogeneous...
This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix −24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and...
STT-RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT-RAM is inefficient in terms of energy and speed compared to SRAM and thus STT-RAM with low retention time (volatile STT-RAM) has been proposed at the cost of scrubbing and error correcting code (ECC). The more frequent scrubbing and stronger ECC are...
Blind Source Separation (BSS) has gained recognition in its application to many different fields of research such as medical, military, and industry fields. Of the many challenges that must be overcome to apply BSS to a real system, implementation restrictions are the most challenging. Software implementations require a significant amount of overhead to make them applicable to real-time systems, and...
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