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This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of −224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N...
This paper proposes a hardware-efficient time-domain scheme to digitally compensate the I/Q imbalance and LO feedthrough (LOFT) of a sub-GHz wideband transmitter for the IEEE 802.11af WLAN. A simple envelope detector is the only analog part. The parameters are updated by Least-Mean-Square and estimated efficiently in time domain by using COordinate Rotation DIgital Computer (CORDIC), saving the training...
This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies...
A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18µm CMOS, the 0.12mm2 ADC consumes 2.16µW at a conversion...
This paper presents a 200MHz 4-phase fully integrated voltage regulator (FIVR) with 6.5nH package bondwire inductors. With an on-chip delay-locked loop (DLL) for phase synchronization, the proposed FIVR employs a cost-effective local ground sensing feedforward control loop for high speed load transient sensing and a ZDS hysteretic feedback control loop for accurate voltage regulation, independently...
A 5.5W mains-powered converter-free LED driver for general lighting application is presented in this summary for the university design contest. The driver is superior to its switching converter based counterparts as it does not require any bulky and expense magnetics or electrolytic capacitors. In addition, the driver is able to significantly reduce the flicker at light output with a quasi-constant...
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising...
This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-µm CMOS technology, while one of them...
A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
This paper describes a power-efficient processor for extracting the timing of QRS complex from digitized ECG, based on the hardware-efficient architecture of quadratic spline wavelet transform (QSWT) and maxima modulus pair recognition (MMPR). The processor succeeds in saving the wireless system's power by 6×.
An energy-autonomous, disposable supply-sensing biosensor based on bio fuel cells and a 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter was demonstrated. All-digital and current-driven architecture using zero-Vth transistors enables low-voltage operation and small footprint in cost-competitive...
The key to high performance for GPU architecture lies in massive threading to drive the large number of cores and enable overlapping of threading execution. However, in reality, the number of threads that can simultaneously execute is often limited by the size of the register file on GPUs. The traditional SRAM-based register file costs so large amount of chip area that it cannot scale to meet the...
Spin Transfer Torque Magnetoresistive RAM (STTMRAM) has been recently deemed as one promising main memory alternative for high-end mobile processors. With process technology scaling, the amplitude of write current approaches that of read current in deep sub-micrometer STT-MRAM arrays. As a result, read disturbance errors (RDEs) emerge. Both high current restore required (HCRR) reads and low current...
The spatial and temporal locality of workloads are the root causes for cache designs to overcome the memory wall problem. However, few existing state-of-the-art designs exploit both the two locality features to optimize the memory hierarchies in the area of tiled many-core systems, which losses the opportunities to explore more performance improvement. To address this problem, an adaptive spatial...
OpenMP is increasingly being adopted by current many-core embedded processors to exploit their parallel computation capabilities. Unfortunately, current run-time implementations of the latest specification (v4.0) are not suitable for processors relying on small and fast on-chip memories, due to its memory consumption. This paper proposes an OpenMP4 run-time that reduces the memory consumption while...
Data integrity is important. One way to protect data integrity is attaching an identifying tag to individual data. The authenticity of the data can then be checked against its tag. If the data is altered by the adversary, the related tag becomes invalid and the attack will be detected. This paper studies an existing tag design (CETD) for memory data in embedded processor systems, where data that are...
A Printed Circuit Board (PCB) provides the backbone for the interconnection of diverse electronic components into an electronic system. Unfortunately, the increased use of untrusted third-party PCB design/fabrication facilities and the long, distributed, supply chain of a PCB makes it extremely vulnerable to variety of integrity violation attacks, primarily different forms of counterfeiting, including...
Employing fault tolerance often introduces a time overhead, which may cause a deadline violation in real-time systems (RTS). Therefore, for RTS it is important to optimize the fault tolerance techniques such that the probability to meet the deadlines, i.e. the Level of Confidence (LoC), is maximized. Previous studies have focused on evaluating the LoC for equidistant checkpointing. However, no studies...
Internet-of-Things (IoT), wherein sensor nodes of different types are used to monitor different objects, are expected to be used in many critical domains. However, hardware Trojans, which are malicious modifications implanted in individual nodes, may utilize the wireless connection facility to leak confidential information or to collude with each other to cause catastrophic failures in the IoT. To...
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