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In this paper, a digital image enhancement using discrete cosine transform (DCT) based matrix homomorphic filtering method is presented. First, the DCT is used to design matrix filter with prescribed ideal response. Because the closed-form solution is obtained, the filter coefficients are easily computed. Then, a digital image enhancement method is proposed by using matrix filter and homomorphic filtering...
In this paper, a hardware-efficient folded SC polar decoder based on k-segment decomposition is first proposed. The proposed k-segment scheme employs (k – 1) N1/k-bit decoders to implement the original N-bit decoder, and reduces the number of mixed-nodes from (N – 1) to (k ă 1)( N1/k – 1) with slightly increased latency. In addition, pipelining technique, partial parallel processing, and pre-computation...
Digital images are distorted by a variety of processes. Thus we need objective image quality assessment (IQA) equivalent to subjective assessment. Several objective IQA methods have been proposed, and recently a combination method has been derived successfully. The combination technique is able to assess distorted images correctly. However, it is weak against Meanshift images. In this paper, we propose...
Recent hardware implementations of fully homomorphic encryption (FHE) exploit very high cardinality arbitrary moduli sets to parallelize large integer arithmetic. However, the benefit they gained are heavily offset by the slow residue-to-binary conversion due to the large modulo operations and limited number theoretic properties of arbitrary moduli. This paper presents a fast residue-to-binary (R2B)...
A key challenge in the design of Internet-of-Things sensors, specifically those powered by energy harvesters, is to minimise the power consumption and realize energy-scalable operation to meet the requirements of the variable power source. This paper proposes an ultra-low power Decimation-in-Time (DIT) radix-2 butterfly arithmetic block for an FFT processor, designed using a bit-serial architecture...
This paper shows a novel estimation algorithm based on the outer product expansion with lower norms for the background noise. We have proposed a blind source separation using an outer product expansion with L1 norm minimization. The effectiveness of outer product expansions for artificial signals and an electromagnetic wave data was represented. However, the estimation performance is decreasing with...
This paper presents a low-power and real-time noise reduction (NR) algorithm using 18-band 1/3-octave quasi-ANSI filter bank for binaural hearing aids. With aids of binaural cues and minima controlled recursive average (MCRA) approach, the proposed NR algorithm consists of a directional mask and an estimated mask. The directional mask exploits the interaural time difference (ITD) together with the...
A digital low dropout regulator (D-LDO) manages to operate at low voltage and scale with process. But, the tradeoff between current efficiency and transient response speed limits its applications. In this work, a coarse-fine-tuning technique with burst-mode operation is employed to advance this trade-off. Once the output voltage under/overshoot is detected, the power MOS array changes with x16 unit...
This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining...
This paper presents a digitally assisted low dropout (LDO) regulator with switched-bias current for internet-of-things (IoT) devices. The operation scenario and system requirements of the IoT devices are analyzed and discussed first. Then, a dedicated dynamic voltage scaling scheme for the very low duty cycle operation is introduced. Then, an LDO regulator with digitally controlled bias current is...
Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state...
An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating...
Digital low dropout voltage regulators provide digital process synthesiz ability, fast transient response and performance adaptation but lack steady state voltage regulation performance. To overcome this lack of steady state accuracy due to limit cycle oscillations, a hybrid low dropout voltage regulator topology designed in 130 nm CMOS process is presented. In the proposed topology, the operational...
By adding a Miller frequency compensation to the conventional LDO circuit that combines the super source follower and the voltage spike detection, a low-power LDO circuit is proposed to drive the load capacitance up to 10 pF with a fast load regulation. The LDO circuit converts a 5 V input to a 3.3V output, consumes 26 μA, and settles in 75 ns at a 10 mA load current step in 1ns.
Uncovering human mobility patterns is of vital importance to the widely practical applications ranging from urban planning to epidemic controlling. Although numerous previous studies regarding human mobility patterns have been carried out to statistically characterize the dynamics of human mobility in both empirical analysis and modelling approach, research on the level of driving factors of mobility...
Cascading failures happened in power grids degrade the robustness of such complex systems. In the cascading process, links can be critical for the propagation of failures. Then It is possible that switching off some links may help the network improve its robustness. In this paper, with the consideration of both the electrical characteristics and complex network structure, we try to assess how the...
Much prior work has demonstrated that the underlying network topology of communication networks is highly relevant to the intended communication performance of the networks. For reliable and efficient traffic transmission, the traffic load distribution in the network should be uniform and the average data transmission distance should be short. In this paper, we aim to find the optimal network topology...
In this paper, we study the effect of traffic generation patterns on traffic performance of complex networks. We consider a generic type of networks consisting of two kinds of nodes: hosts and routers. In this kind of network, the traffic performance is closely related to the traffic generation pattern which is determined by the hosts' locations. We evaluate the performance of six kinds of methods...
In this study, we investigate chaos propagation in coupled chaotic circuits with multi-ring combination. We compare the different coupling combination. These models are coupled chaotic circuits when one circuit is set to generate chaotic attractor and the other circuits are set to generate three-periodic attractors. By using computer simulations, we have observed that the chaotic attractor is propagated...
In this study, we investigate synchronization in complex network with two hubs by using parametrically excited van der Pol oscillators with parameter mismatch. By means of computer simulation, we confirm various change of synchronization probability in complex network, and observe effects on synchronization probability by changing structural metrics (degree and path length) in subset of the nodes...
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