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The exploration of different design configurations of dynamic dataflow programs executed on many-core or multi-core platforms is, in general, a very difficult task. Determining a close-to-optimal partitioning, scheduling and buffer dimensioning configuration, when associated with a performance optimization function, belongs to the class of NP-complete problems. In order to explore the space of feasible...
Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using a dual-supply voltage (dual-Vdd) approach. In order to achieve an improved power efficiency, we have applied a new type of pipelining to reduce the number of gates need to be assigned to the high supply voltage given a target delay. Compared to the standard pipelining and the standard...
Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations...
Carbon nanotubes (CNTs) present themselves as a viable material for on- and off-chip interconnect material due to their unique electrical, thermal and mechanical properties. The electro thermal properties of CNTs, including high Young's modulus, resiliency and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for local and global on-chip...
Resistive random-access memories (RRAMs) operate with low power dissipation, low cost-per-bit, and high endurance, and are suitable for integration in crossbar arrays in 3D chips. These attributes make RRAM devices well-suited for a variety of applications ranging from novel processor architectures and high-density memories to neuromorphic computing and neural networks. We employ a unique suite of...
Thermoelectric properties of graphene and graphene-based nanostructures have recently attracted great attention from both physics and engineering communities. However, to make graphene a good thermoelectric material, two important issues must be overcome, i.e. (i) its gapless character, which leads to a poor value Seebeck coefficient in pristine graphene and (ii) its high thermal conductivity that...
This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents...
Operating in the Near Threshold Voltage (NTV) region improves the energy-efficiency of CMOS circuits by an order of magnitude. However, the number of hold-time violations significantly grows by scaling the supply voltage to the NTV region due to the increased delay variations. Furthermore, the conventional hold-time fixing approaches based on corner analysis are not applicable to the NTV region. In...
Energy-efficient, low-cost wireless sensor nodes (WSN) will be a key component in enabling the Internet of Things. The main challenges for these nodes are energy efficiency, cost and ease of software development. At ARM Research, we investigate sub-threshold and near-threshold systems using a custom-built 65nm CMOS ARM Cortex-M0+ platform. This paper will present key challenges of implementing an...
Recently, manycore architectures are widely adopted for providing the increasing throughput demands and requirements imposed by software complexity and volume explosion. At the same time, the threat of Dark Silicon points to the direction of energy efficient platforms. Near Threshold Computing (NTC) paradigm has recently emerged as the premise of energy efficient operation at the expense of performance...
Advanced analysis on transient noise simulation was performed and the limitations on estimating accurately MOSFET noise performance were identified. The signal processing theory defining transient noise was examined and SPECTRE based simulation benchmark tests using an RF 65 nm CMOS process available by TSMC, were performed on flicker, thermal and gate induced CMOS noise performance, validating transient...
In this paper the effect of high-performance techniques for high speed applications in secure cryptographic implementations is studied. The use of dual pre charge logic styles with fine-grained pipelining with an overlapping three-phase clock scheme is studied, also including a correct distribution of the clock signal in the cryptographic implementation. To make this study, four different implementations...
Dynamic Voltage and Frequency Scaling (DVFS) is widely used in today's mobile devices. Commonly adopted OS level DVFS policies usually operate with high sampling and adjustment frequency in order to compensate for the lack of information from applications. In this paper, we consider the application of video decoding and propose a method that enables DVFS at a coarse time granularity by taking advantage...
In the nano scale era, the upcoming design challenges like dark silicon, power wall, and memory wall have prompted extensive research into the architectural alternatives to the general purpose processor. Coarse Grained Reconfig-urable Architectures (CGRAs) are emerging as one of the promising alternatives. Commonly, CGRAs are composed of a computation layer and a memory layer. Tempted by higher platform...
An in-storage deduplication based on a resistive content addressable memory (ReCAM) is proposed. The ReCAM native compare operation is used to find duplicate data blocks in a fixed number of cycles. The performance of ReCAM based in-storage deduplication is compared to Solid State Drive (SSD) based in-line deduplication performed in CPU and DRAM, showing an average 100× higher throughput at roughly...
This work evaluates the static power component of static CMOS logic gates. Simulations at the electrical level (SPICE) were performed to evaluate the transistors stacking effect on different manufacturing processes using a group of logic gates. The transistors stacking effect was selected because it can be easily incorporated into a transistor network design or library-free approach that has also...
Almost all previous works and methods on schedulability test employ offline methods. In some cases such as designing energy-efficient real-time systems we need to test schedulability at run time. The key challenge while applying energy efficient design techniques on real-time systems is to guarantee that no deadline will be missed. We propose a method for run-time schedulability check of real-time...
Process-induced mechanical stress has been known as a technique to boost carrier transport of transistors. Basically, stress affects leakage consumption, threshold voltage, and mobility by making changes in band structure of silicon. Stress-enhancement techniques are highly dependent on layout structure. In past years the device parameters have been modeled versus some of the layout parameters incorporating...
In this work, we present a multiscale simulation platform as a viable tool to engineer novel electron devices. The tool connects the specific material properties (as atomic defects, interfaces, material morphology) to the electrical behavior of the device, representing a virtual space for the design of novel electrons device purposely exploiting atom-electron interactions. This simulation platform...
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