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The Conference Proceedings contain papers accepted for the 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) held from 22 to 26 May 2017 at the Grand Hotel Adriatic Congress Centre and Hotel Admiral in Opatija, organized by MIPRO Croatian Society and technically co-sponsored by IEEE Region 8. The authors are from industry, education,...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Circuit design courses in general, and microwave circuit design courses as a subspecialty, have been taught over many decades. It is relatively recently, however, that instructors have started experimenting with more modern approaches to in-class and out-of-class instruction. In our attempt to make instruction more effective we have turned to: a) utilizing classroom interaction systems and collaborative...
The ever-shrinking world of semiconductors has always challenged the interplay of tool capability, process integration, and characterization. The fine line between structural or electrical success and failure has steadily been redefined from microns to nanometers with leading edge technology using terms with the likes of angstroms and layers of atoms. Failure modes at these nodes become increasing...
Our experiences in teaching digital circuit design at university level indicate that students find it difficult to understand programmable logic devices (PLDs) such as PALs, PLAs, GALs and FPGAs. This is mainly due to the complexity of the topic and the lack of tools that visualize the inner workings of PLDs and enable students to modify and inspect individual components. The majority of publicly...
Copper voids are critical defect issues in the metal lines. Massive voids cause functional fails and the smaller ones that do not cause any function fails carry high risk of failing later in life. They are threats to product lifetimes. In this work, we discuss a process for dual damascene copper for metal lines capable of causing surface voids.
For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In...
The course “Electronics 1” is taught at undergraduate level and covers broad area of electronics starting from the physics of semiconductors to the complex electronic system such as operational amplifier. This course is obligatory for sophomore students enrolled in Electrical Engineering and Information Technology undergraduate program as well as in Computing undergraduate program. Due to the course...
Power and Advanced BiCMOS technologies use deep trench architecture to reduce capacitance and leakages that are enhanced by high electric fields and high current applications. In this paper, a power and an advanced BiCMOS technology with deep trench architectures used micro Raman spectroscopy to identify non-uniform stress regions in the circuit. Using this information, architectural changes were...
In this paper, an approach to automated formative assessment of procedural knowledge is described and evaluated. While assessment and representation of conceptual knowledge using visual aids such as of concept maps has often been analyzed and discussed in the literature, significantly less attention has been given to assessment of procedural knowledge. The approach described in this paper is based...
Electroplating for the sub-50 nm pitch back-end-of-line (BEOL) interconnect metallization has become increasingly challenging mostly because of marginal seed coverage, inadequate plating process and/or chemistry, the limitation of scaling the barrier-liner and seed thickness. In this study we show how inadequate plating due to the marginal seed caused degraded via open yield along the perimeter of...
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