The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
A cost-efficient framework for executing life-time dependability procedures is presented in this paper. The proposed framework relies on distributed sensors and actuators (embedded instruments) for self-awareness and adaptation, where the IEEE 1687 standard (iJTAG) is utilized for the dependability communications and the on-chip access of the instruments.
In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2. Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length...
Reassuring fault tolerance in computing systems that contain FPGA devices is the most important problem for mission critical space components. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper, we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded with on-demand three level...
The relation between amplitude and duration of the current pulse induced by a high energy ionizing particle has been proposed as a criterion for evaluating the SET and SEU robustness of integrated circuits. This criterion has advantage over the widely accepted critical charge concept in the sense that it is less dependent on the current pulse shape. However, to the best of our knowledge, there is...
Fraunhofer IMS develops and fabricates far-infrared focal plane arrays (IRFPA) using microbolometers with a pixel pitch of 17μm technology realized on top of a 0.35 μm CMOS readout integrated circuit (ROIC). The microbolometers are encapsulated by a Chip-Scale-Package (CSP) to ensure a high quality vacuum level. The CSP is realized by placing an infrared transparent lid above a solder frame surrounding...
Test point insertion methods to reduce the number of test patterns at register transfer level are required for the adaptability of traditional VLSI design flows and the reduction of time to search test point locations. In this paper, we propose a design-for-testability method at register transfer level to enable operational units as many as possible to be concurrently tested in scan testing. Using...
The adoption of multi- and many-core processors in avionic applications is still limited by certification concerns, mainly due to non-deterministic behavior. In this paper, we review requirements of avionic applications, and we identify some of the critical issues that they are going to face on many-core processors. We then propose a preliminary version of a network-on-chip architecture suitable for...
A method is presented that guides diagnosis using multiple transition faults on sensitized embedded segments. Suspect faults are eliminated with non-enumerative operations and non-pruned faults are ranked. The approach also considers speed-ups on gates. Experimental results demonstrate the scalability of the proposed approach and its effectiveness in fault diagnosis.
In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented.
Ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties. In this paper, we introduce a novel methodology to estimate the vulnerability of sequential circuits to soft errors at gate level. A new probabilistic modeling of SET propagation is proposed, which reduces the complexity of unrolling sequential circuits. This approach enables a multi-cycle error propagation...
A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for...
The main memory in today's systems is based on DRAMs, which may offer low cost and high density storage for large amounts of data but it comes with a main drawback; DRAM cells need to be refreshed frequently for retaining the stored data. The refresh rate in modern DRAMs is set based on the worst-case retention time without considering access statistics, thereby resulting in very frequent refresh...
In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving...
Post-silicon validation is concerned for discovering design errors that escape to the silicon prototypes. Recent research efforts have shown how to reuse the constraints from pre-silicon verification to support post-silicon constrained-random validation. The objective is to subject the prototype to a large volume of random, yet functionally-compliant stimuli. In this paper, we present a new method...
With increasing use of electronic systems in vehicles for managing critical functionality, the requirements for safety in automotive chip architectures are becoming mandatory. Thus, automotive chips must provide functional safety capabilities in addition to the general functionality. Augmenting logic and memory BIST (Built-in Self-Test) solutions with new features is one of the options to facilitate...
In-field test of electronic devices is becoming increasingly important due to the wide adoption of electronic systems in safety-critical applications. Hence, it is crucial to devise and deploy effective solutions supporting the test during the operational phase of all the components of an electronic system, including the memory modules embedded in a SoC. Some key aspects include the possible reuse...
The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated...
Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. Arbiter PUF is a typical PUF, but is threatened by modeling attacks. To resist attack, XOR arbiter PUF employs multiple basic arbiter PUFs and XOR their response bits to generate the final response bit. However, its low reliability not only limits its applications, but also leaks information to enhance...
In this paper, we propose NBTI/PBTI (negative/positive bias temperature instability) tolerant arbiter PUF (physical unclonable function) circuits and evaluate its performance. The PUF is a technology for generating cryptographic keys and authenticating by utilizing physical characteristics, such as electronic delays, built in the devices when they were manufactured. It can perform encryption and authentication...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.