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Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature...
Efficient and smart techniques for analog data acquisition and processing may play crucial role in the design of miniature wearable devices, meant to continuously record, process and wirelessly transmit vital physiological parameters for real time health monitoring. In this work we propose a low-power, all-analog processing unit for an MPG (magneto-plethysmograph) based wearable device, which is meant...
This paper focuses on the design and analysis of multi-stage noise-shaping (MASH) sigma-delta modulators. Fundamentals and properties of MASH modulators are discussed. A detailed methodology on analyzing continuous-time MASH (CT-MASH) modulator based on the impulse invariant transformation is also described. Two fabricated design examples are discussed: a 130 nm CMOS CT-MASH 4-0 employing a digital...
A 7GS/s 6b sub-ranging ADC is implemented in 32nm CMOS SOI with reconfigurable comparators, and adjustable input differential pairs are exploited to change converter characteristics for hardware-based cybersecurity. To achieve low-power consumption at high-speed operation with small-size transistors, an on-chip calibration to reduce process mismatches is utilized in the design. The presented ADC achieves...
A novel offset calibration technique with fast convergence rate for high-speed dynamic comparators is presented. The circuit utilizes a multi-rate charge pump circuitry to speed up the calibration process while maintaining the precision which leads to better energy efficiency. The circuit is designed in a 0.13μm CMOS process. Based on Monte-Carlo simulation results the comparator achieves 183.1μV...
This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency...
An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
In this paper a novel wideband transformer-based CMOS VCO with simplified topology and digital amplitude calibration is proposed. Owing to the digital amplitude calibration, the immunity to process, temperature and voltage supply variations is improved and a considerable reduction of power consumption is observed (i.e. over 25% in normal process corner, supply voltage and temperature). Besides, the...
This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method...
A robust calibration and supervised machine learning reliability framework has been developed to aid the circuit designer in the design and implementation of reliable digitally-reconfigurable self-healing RFICs. For calibration algorithm performance and reliability validation, we advocate the use of surrogate modeling, a supervised machine learning technique, which offers a significant reduction in...
This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array...
This work reports a frequency-agile receiver front-end for rapidly changing channels. The receiver includes a programmable low noise amplifier (LNA) that can be tuned from 4.3 to 5.7 GHz using an all-digital phase-locked loop (ADPLL). It also includes a power detector, a 10-bit SAR ADC, and a closed-loop system to dynamically optimize the matching of the LNA.
This paper presents a new approach to approximate various complex arithmetic functions for applications in wideband RF transceivers by using stochastic computing based on the piecewise linear (PWL) approximation. The optimized design parameters for PWL approximation are chosen by an optimization algorithm targeting the best tradeoff between hardware complexity and approximation accuracy. Then, this...
A technique generating timing skew resistant time-interleaved signals is proposed. With a simple logic function, all the timing alignment critical signals' falling edges or rising edges can be trimmed by the master clock without introducing charge injection. Thus the generated time-interleaved signals are resistant to timing skew. When these time-interleaved signals are applied to a time-interleaved...
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