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Mobile communication and navigation devices have fueled the demand for low power implementations to enhance battery life. A critical aspect of reducing power in these devices is the efficiency of the process of converting power from the battery to the various loads in the system. This makes high-efficiency DC-DC switching power converters a natural candidate for such task. Unfortunately, however,...
Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel...
This paper presents a method for calculating the semiconductor losses in asynchronous and synchronous PWM buck converters when operated as a fixed-VI, fixed-RL, variable-Vo dynamic power supply. Equations are derived for MOSFET switching and conduction losses in both circuits, as well as diode conduction and forward-voltage losses. This work also compares the two topologies from the perspective of...
Compressive sensing (CS) is a recent signal processing paradigm that exploits the inherent sparsity in input signal through data compression before wireless transmission. Recent CS implementations have shown impressive energy-efficiencies with good signal recovery but require apriori sparsity estimation and are thus not adaptable dynamic IoT environments resulting in loss of accuracy. This paper describes...
A new headphone driver IC based on a switching output stage in continuous conduction mode is described. The driver uses a sliding-mode peak-valley control scheme to regulate the inductor current. The output stage is switched between the battery voltage and the output of an integrated non-regulated inverting charge pump, and a second-order loop filter is used to regulate the output voltage. The system...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
This paper investigates a high power factor switch-based wireless power transfer front-end circuit for heterogeneous systems. This circuit uses an integrated switching rectifier, implemented in 0.18um 1.8V/5V CMOS process. An integrated pair of phase synchronizers is used to align the waveshape of a wirelessly-coupled sinusoidal voltage source in the receiving coil to the corresponding conducting...
In this paper, we illustrate, through examples, a novel graph-based modeling technique of two-state (on-off) PWM power converters. Differential equations of power converters are derived by inspection, based on two incident matrices, β(u) and J(u). We associate to each circuit (on, u = 1, or off, u = 0, circuits) a digraph and identify current loops (inductor-capacitor, voltage source-inductor, current...
In this paper, an analytical approach is proposed for solving a special set of transcendental equations, which are often encountered for eliminating harmonics in converters. Typically, numerical solutions are used for solving the transcendental equations. The disadvantage of numerical approach is overhead in computational effort as it requires a PC with expensive software and solution time can also...
This paper presents an original and unique embedded FFT hardware algorithm development process based on a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in a Kronecker Pease FFT hardware implementation. This is coupled by a procedure to perform automatic code generation of Kronecker FFT cores. The...
The Sun has the potential to provide 89,300 tera Watts of power to our planet. Our ability to convert even a fraction of this energy for human use makes a significant impact on current energy generation and consumption trends. World-wide we now add more renewable energy capacity every year than (combined) fossil fuel energy capacity. Solar panels provide a reliable, renewable, non-polluting energy...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
Memristor technology is receiving an increased attention as a potential solution to meet the scaling demands in integrated circuit design. Memristor provides advantages like high-density, low-power, non-volatility and good scalability. In this paper, an 8-bit iterative full adder design is proposed that uses space-time based circuit notation. It uses stateful logic with memristive nanowire crossbar...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
This paper presents a detailed noise and non-linearity analysis of a 10-bit 1.2Vppd 50MS/s charge-injection based SAR-ADC designed in a 65 nm low power process. Being more area-efficient in contrast to a conventional capacitor DAC, a charge-injection-cell-based DAC allows to reuse its DAC cells during binary search. Based on extensive calculations and transistorlevel simulations, the charge-injection...
This paper presents a new scheme for enabling wide input voltage range for SAR (successive approximation register) ADCs. Precision ADC usually favors large input voltage range (>3V), while a push for higher throughput often calls for the use of low voltage devices in fine lithography. There are elegant solutions to bridge the gap. Recently a new type of SAR ADCs using passive charge sharing technique...
Pulse-width modulation (PWM) has been extensively used in switched converter systems, and recently in RF applications, due to an increased interest in all-digital transmitters. These architectures employ high efficiency switched-mode power amplifiers (SMPA), where PWM is commonly used to generate the PA driving signal. However, digitally implemented PWM introduces large amount of in-band distortion,...
This paper presents a static non-linearity correction technique exemplary applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in 180 nm CMOS. The proposed technique proves for the first time, that an undesired power supply and package resistance can be turned into a benefit by canceling non-linearity effects introduced by the MOSFET switches within the source...
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