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Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Memory protocol commands and firmware features for storage solutions may function correctly by themselves, but due to implicit cross-feature dependencies they may exhibit incorrect behavior when exercised in combination with other features or commands. How can we efficiently use a set of standalone per-feature tests to test the cross-features dependencies? We define an algorithm that is based on greedy...
In the system on chip design process, functional validation is regarded as one of the main challenges. One sub problem in functional validation is proving the unsatisfiability of certain properties such as the reachability of some assertions or code blocks. In this work, we present a induction-based bounded model checking technique using a Satisfiability Modulo Theories (SMT) solver for proving the...
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
Ensuring the correctness of industrial smart displays applications is fundamental given the requisites concerning reliability and safety demanded by their deployment in industrial plants. However, verification of Human-Machine Interaction applications usually requires an operator using them. This paper presents an approach to automatically verify a set of properties on HMI applications for industrial...
Cyber-Physical Systems (CPS) are composed of computation, networking, and physical processes. Model-based design is a powerful technique to apply mathematical modeling in CPS design. A model of a physical system is the description of variations in some aspects and properties of the system such as motion, velocity, and pressure. The variations of physical quantities such as motion, velocity, and pressure...
We present an approach to allow a non-programmer develop simple cyber-physical systems using natural language text to specify the system behavior. Users specify the relationship between sensor inputs and actuator outputs through a series of conditional sentences written in English. The relationships are used to generate code for an Arduino development platform and to produce a netlist connecting the...
Post Silicon Validation is critical step in order to deliver quality microcontroller chips to customers but is increasingly becoming complex and time consuming process as the design size is increasing. Due to increased number & diversity of design intellectual property, microcontroller post silicon validation has moved towards customized validation concept and hardware setup for individual design...
Through silicon via (TSV) based 3D integrated circuits (ICs) have become a popular approach to revive Moore's law. However, the reliability of a TSV is an important issue, as a faulty TSV can result in the failure of the entire 3D IC. Most of TSV faults can be detected during the testing process, however, detecting TSV aging faults during the testing process is impossible. Certain mechanisms are required...
Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer...
Hardware Trojans (HTs) have been generally inserted at the lower levels of the digital system design and fabrication process, where, due to the high complexity of the hardware model, their detection is more difficult. However, RTL models are becoming more and more complex, making difficult the identification of malicious behaviours also at this level. Unfortunately, only a few verification techniques...
The rapidly growing design complexity has become a big obstacle and dramatically increased the time required for SystemC simulation. In this case study, we exploit different levels of parallelism, including thread- and data-level parallelism, to accelerate the simulation of a Bitcoin miner model in SystemC. Our experiments are performed on two multi-core processors and one many-core Intel(g) Xeon...
The purpose of this paper is to prove the accuracy and reliability of a novel FPGA-based tracker of the muscle conduction velocity in ordinary dynamic contractions, such as during the gait. In this work, we present the digital signal-processing unit. The system performs the acquisition of the needed bio-signal, from 4 wireless surface EMG electrodes. The acquired data undergo to a dynamic bit-stream...
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and closely spaced nature of TSVs has made them seriously prone to coupling capacitances between TSVs, increasing the probability of crosstalk faults. To reduce crosstalk faults in 3D ICs, this paper proposes a dynamic...
Here we consider one special situation for approximate computing. Given a specification, S, in a truth table and its corresponding multi-level logic circuit implementation, I, S is changed to S' by only changing the truth table value for exactly one minterm from 0 to 1 or 1 to 0. We would like to transform I into I' in such a way that I' is equivalent to S' This is a sort of basic operations for approximate...
Although the Moore's law is slowing down in terms of technology node scaling, researchers are inventing new methods to keep the design productivity on the rising trend. As a consequence, the complexity of hardware designs will continue to grow, which results in further hardening of functional verification. Assertion based verification is well established and proven to be an effective RTL verification...
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