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A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
With the growing demand for mechanically flexible electrical systems and the increasing level of integration of electrical assemblies, hybrid build-ups combining polymer substrates and ultra-thin flexible silicon chips (system-in-foil) are getting more and more important. These systems need thin chips which maintain their functionality even in bent condition as well as reliable handling and assembly...
The paper describes an experimental approach to determine mechanical properties of copper that have been used in technical application, e.g. PCB copper traces. The investigations focus on an experimental design to determine the mechanical behavior of real PCB copper traces. In the first step the differences between idealized specimen and representative specimens for real PCB copper traces will be...
Silver sintering is a promising emerging microelectronic assembly technology. In this paper sintered silver attachment joints of silicon dies have been studied. It has been pointed out that in pressureless process conditions porosity can disappear of some zones of silver sintered attachment joints. The link between densified zones and the thermo-mechanical stress has been demonstrated. Densified zones...
The process of singulating IC packages such as Quad Flat Pack No-Lead (QFNs) by either a sawing or punching operation results in exposed copper on the sidewalls. This exposed copper surface can oxidize leading to poor or no solder wetting up the sidewall during the assembly operation. The consequence of this oxidized copper surface is either incomplete or no solder fillet formation during the PCB...
Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct...
This work presents the development of a highly integrated power switch, based on 70μm thin IGBTs and diodes rated at 600 V. The integration relies on advanced ceramic substrate technology, featuring double-etched patterned copper tracks for a fully bond-wire-less double-sided cooling packaging solution; viases are also used in the ceramic substrates for vertical current conduction, which enables the...
We have developed mechanically soft and conformable light emitting diode (LED)-implemented fabric for the applications to the three dimensionally complicated shapes of furniture, tents and ceilings by transforming the shape of the lighting fabric. The developed LED fabric is assembled by the process in which the LED-mounted 5 × 20 mm pieces of printed circuit board (PCB) is firstly soldered to 2 cm...
This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended...
Since about 15 years back, there were several attempts to increase power density by double-sided cooling of power semiconductors, mostly by a sandwich stack with two DCBs. This paper gives an overview over the developments and approaches over the last years and some results of another project concerning double sided cooling.
In this work, the influence of the copper pad geometry on the reliability of printed circuit board/ball grid array (PCB/BGA) assemblies under drop impact is assessed. The method employed is based on drop experiments combined with finite element simulations. For the experimental part, various test PCBs with three different pad designs were manufactured and tested under drop impact loading conditions...
The plasma surface activation was applied to the thermal-compression bonding of chips and substrates. An Ar gas was selected to perform the physical plasma treatment on the bonding surface of Au bumps and Cu electrodes. This plasma-activated technology was expected to remove the surface contaminants, and then to reduce the bonding barrier for chips and substrates assembly. The experimental results...
The stacked memory device that combined eight single memory units in the vertical direction was investigated in this study when the device was subjected to the random vibrations. The fine computational model of the stacked memory with eight units assembled on board-level was built by ANSYS. The modal analysis was carried out first. By applying the power spectrum according to the GJB-548B standard,...
In this paper, a multi-conductor transmission line (MTL) model of a spacecraft harness is presented. Some of the practical issues that occur in the modeling process are discussed, and typical values of the model parameters for a particular example are given. Finally, the model results are validated with measurements.
This paper presents the first demonstration of a high-throughput die-to-panel assembly technology to form Cu interconnections without solder at temperatures below 200°C. This interconnection technology, previously established with individual single-chip packages on both organic and glass substrates, at pitches down to 30μm, is brought up to a significant manufacturable level by two major innovations:...
The stacked memory device that combined eight single memory units in the vertical direction was investigated in this study when the device was subjected to the random vibrations. The fine computational model of the stacked memory with eight units assembled on board-level was built by ANSYS. The modal analysis was carried out first. By applying the power spectrum according to the GJB-548B standard,...
The plasma surface activation was applied to the thermal-compression bonding of chips and substrates. An Ar gas was selected to perform the physical plasma treatment on the bonding surface of Au bumps and Cu electrodes. This plasma-activated technology was expected to remove the surface contaminants, and then to reduce the bonding barrier for chips and substrates assembly. The experimental results...
Emerging 2.5D and 3D package-integration technologies for mobile and high-performance applications are primarily limited by advances in ultra-short and fine-pitch off-chip interconnections. A range of technologies are being pursued to advance interconnections, most notably with direct Cu-Cu interconnections or Cu pillars with solder caps. While manufacturability is still a major concern for the Cu-Cu...
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12"/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer diameter...
The applications of inertial sensors have a wide variety in terms of accuracy and costs. A new technology approach is joining higher sensor accuracy and lower production costs by using a new Interposer / sensor interconnect technology applied on 300mm wafer diameter without changing the sensor element itself. The higher accuracy is mainly covered by a multiple point program: (1) stress less assembly...
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