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FPGA-based accelerators are becoming first class citizens in data centers. Adding FPGAs in data centers can lead to higher compute densities with improved energy efficiency for latency critical workloads, such as financial applications. However FPGA deployment in datacenters brings difficulties both to application developers, and cloud providers. Application writers need to deal with the interfacing...
P4 is a domain specific language designed to define the behavior of a programmable data plane. It facilitates offloading hardware-suitable Network Functions (NFs) to a data plane. Consequently, NFs can maximally benefit from high performance of hardware devices, meanwhile more CPU power can be reserved for user applications. However, since the programmable data plane provides an NF with an exclusive...
ExpEther is a virtualization technique that extends PCIe of a host CPU to Ethernet. Since all devices connected by ExpEther can be treated as if they were directly connected to the host, a multi-GPU system called GBU-BOX that connects a number of GPUs virtually to a host can be easily developed. However, the smaller bandwidth of Ethernet compared to PCIe often bottlenecks the system. An on-the-fly...
An outstanding practical challenge is how to orchestrate applications end-to-end across distributed cloud computing and software-defined network infrastructures. In this demo we demonstrate how end-to-end orchestration is done in the SAVI testbed, a multi-tier cloud composed of Smart Edges distributed across Canada. Our Smart Edges integrate OpenStack and OpenFlow based on the concept of Software-Defined...
Computing performance and scalability are essential ingredients in modern data centres offering cloud services. Field Programmable Gate Arrays (FPGAs) provide a promising opportunity to improve performance, security and energy efficiency because their hardware architecture can be adapted directly to the application. In this paper we present the development of our FPGA cloud architecture, beginning...
Malicious stealth software can detect being executed in a virtual machine and thus behave differently. If the system virtualization however is moved to the hardware level, the malware is fooled and can be identified and monitored. This paper gives an overview of requirements for a hardware supported virtualization facility implemented on an FPGA. These requirements are examined along the lines of...
Integrating FPGAs into clouds or data centers allows easy access to such reconfigurable resources and provides a promising opportunity to improve both performance and energy efficiency of such systems. Although currently the use of FPGAs as hardware accelerators and especially in clouds is mainly a topic of research, the integration of reconfigurable virtualized resources will become a task of growing...
The FlexTiles Platform has been developed within a Seventh Framework Programme project which is co-funded by the European Union with ten participants of five countries. It aims to create a self-adaptive heterogeneous many-core architecture which is able to dynamically manage load balancing, power consumption and faulty modules. Its focus is to make the architecture efficient and to keep programming...
Today, ARM is becoming the mainstream family of processors in the high-performance embedded systems domain. In this context, adding a run-time reconfigurable FPGA device to the ARM processor into a single chip makes it possible to combine high performance and flexibility. In this paper, we propose a low-complexity design of system virtualization running on the Zynq platform. Virtualization of software...
We present a new approach for integrating virtualized FPGA-based hardware accelerators into commercial-scale cloud computing systems, with minimal virtualization overhead. Partially reconfigurable regions across multiple FPGAs are offered as generic cloud resources through OpenStack (open-source cloud software), thereby allowing users to "boot" custom designed or predefined network-connected...
Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints...
This paper presents a virtualization approach for heterogeneous adaptive multi-core systems distributed onto several FPGA-boards. The virtualization layer consists of an adapted embedded Linux kernel and several special purpose operating systems. The benefits are demonstrated with a complex image processing application.
Efficiently managing the parallel execution of various application tasks onto a heterogeneous multi-core system consisting of a combination of processors and accelerators is a difficult task due to the complex system architecture. The management of reconfigurable multi-core systems which exploit dynamic and partial reconfiguration in order to, e.g. increase the number of processing elements to fulfill...
Hardware virtualization is a well known technique in processor based hardware architectures for abstraction of the complexity of an underlying hardware from the programmer. Not only processor based hardware, especially Field Programmable Gate Arrays (FPGA), comes with a high complexity and the exploitation for developers suffer from this fact. Each change in the hardware e.g. through an introduction...
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a field-programmable-gate-array (FPGA) based prototype we show a latency of 970 ns between two machines with our virtualized engine for low overhead (VELO). The FPGA device is directly connected to the CPUs by a hypertransport link. The described hardware architecture is optimized for small messages...
This paper introduces a virtualized FPGA-based accelerator for wire speed scheduling of packet streams under quality of service constraints. This work implements the dynamic window constrained scheduling algorithm and builds upon our previous custom accelerator by adding support for virtualization. This implementation is parametric, permitting tradeoffs between packet decision latency, decision throughput,...
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