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This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency...
This paper designs a reconfigurable video MTD IP core, which established in XUP Virtex-II Pro development system platform. The design takes System Generator for the development tool, which is a system-level modeling tool developed by Xilinx Inc, to built a reconfigurable video MTD algorithm in MATLAB/Simulink environment, which is available for the FPGA platform. Then the algorithm is solidified as...
An efficient VLSI architecture of motion compensation of MPEG-4 is presented in this paper. Aiming at the memory accessing problem of the motion compensation, three special methods were adopted. First, a novel interpolation pixel buffering mechanism and the corresponding parallel interpolation structure were proposed to save the buffering storage consumption of the interpolation pixels distinctly...
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution...
This paper proposes a coarse-to-fine two-level synchronous data acquisition and transmission system for binocular stereo vision, which satisfies strict synchronous requirement of stereo vision.Specifically,this synchronization system design contains: the hardware circuit design based coarse level and the hardware description language (HDL) design based fine level.The former includes synchronization...
This paper introduces the composition and operating principle of the image test signal generator about HDTV based on CPLD, it explains the logic function design in CPLD and the hardware configuration of this system in detail. The signals produced by this generator accord with the parameter standard of video signal interface about our national High Definition Television. Furthermore, programming with...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a technique for reducing the amount of computations performed by H.264 intra prediction algorithm. For each intra prediction equation, the proposed technique compares the pixels used in this prediction equation. If the pixels used in a prediction equation are equal, this prediction equation is simplified...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
H.264 intra prediction algorithm has a high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. The proposed technique performs a small number of comparisons among neighboring pixels of the current block...
In this work the image is segmented effectively based on texture feature by reducing the noise. For effective image segmentation Expectation-Maximization (EM) algorithm based on Gabor filter is used. The EM algorithm is applied on 2D Ultrasonic image of uterus and tested. The Gabor function has been recognized by its multiresolution properties and the precision of locating the texture features in...
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an efficient...
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance reconfigurable hardware architecture of 1BT based multiple reference frame (MRF) ME. The proposed ME hardware architecture performs full search ME...
In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA.
Pedestrian recognition on embedded systems is a challenging problem since accurate recognition requires extensive computation. To achieve real-time pedestrian recognition on embedded systems, we propose hardware architecture suitable for HOG feature extraction, which is a popular method for high-accuracy pedestrian recognition. To reduce computational complexity toward efficient hardware architecture,...
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance systolic hardware architecture for 1BT based ME. The proposed hardware performs full search ME for 4 Macroblocks in parallel and it is the fastest...
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it...
This paper presents PARPIV the design and prototyping of a highly parameterized digital Particle Image Velocimetry (PIV) system implemented on reconfigurable hardware. Despite many improvements to PIV methods over the last twenty years, PIV post-processing remains a computationally intensive task. It becomes a serious bottleneck as camera acquisition rates reach 1000 frames per second. In this research,...
Template matching is a classical problem in computer vision. It consists in detecting the presence of a given template in a digital image. This task becomes considerably more complex with the invariance to rotation, scale, translation, brightness and contrast (RSTBC). A novel RSTBC-invariant robust template matching algorithm named Ciratefi was recently proposed. However, its execution in a conventional...
In this paper, we present an efficient H.264 / AVC Intra 16times16 Frame Coder System. The System achieves realtime performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The...
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