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This paper presents a Sub-block Combination Fractional Motion Estimation (SCFME) algorithm and its architecture for an H.264/AVC video encoder. Unlike typical FME algorithms, SCFME can eliminate the overlapped pixel interpolation, and thus, it can reduce the computational complexity. Compared with the JM reference software, the proposed algorithm can reduce up to 69.75% of the number of pixels for...
The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform background identification on HD images. The proposed circuit is based on the OpenCV implementation, particularly suited to improve the initial background learning phase. Bit-width has...
There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized...
As camera sensor technology has advanced, image sizes have grown and the methods employed to process imagery have become more advanced and complex. For infrared (IR) imaging systems, more processing is typically required than in electro-optical (EO) systems in order to adjust the data so that it is visibly more meaningful or to preserve details that may be lost in compression. JPEG and JPEG2000 typically...
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an efficient...
A new fast line drawing algorithm that is different from the traditional Bresenham algorithm is presented in this paper. A line is treated as an aggregation of several line segments and the Y coordinate differences of candidate pixel points in every step of traditional algorithm are replaced by the length errors of each segments in this new algorithm. Each operation and judgment can generate a line...
A critical step in fingerprint recognition is to skeletonize the fingerprint image for minutiae extraction, which is recognized as "thinning" in image processing. The speed and reliability of the thinning process are important for the whole fingerprint identification system. In this paper, to accelerate the thinning process, a fast hardware thinning algorithm is implemented on the Xilinx...
Fingerprint identification is an important biometric technique for personal identification. Most of the automatic systems of fingerprint recognition are based on matching of fingerprint minutiae. In this paper, we described a method that reduces the complexity of computations and extract the minutiae from binary image with appropriate speed. In this paper a new hardware scheme is presented which is...
Watershed transformation is a powerful technique that can be efficiently used for image segmentation. In this paper, we implement a watershed based segmentation algorithm on a Virtex II Pro platform. The main contribution of this work is the low execution time and minimal internal FPGA consumed resources. The proposed architecture includes two main blocs. First, a gradient of the image is generated...
The latest H.264/AVC standard can provide us superior coding performance. However, the new technique also brings about complexity problem, especially in motion estimation (ME) part. In hardware, the pipeline stage division of H.264 based ME engine degrades many software oriented complexity reduction schemes. In our paper, we propose one VLSI friendly fast ME algorithm. Firstly, pixel difference based...
Background maintenance is a complex problem due to varying scene conditions. Typically, a single algorithm cannot handle the complex scene changes that occur in visual surveillance applications. Also complex background modelling techniques, for example mixture of Gaussians have a high computational and communication demand compared to simple techniques such as a uni-model background model or simple...
In this work, the influence of the content of algorithms for primary processing of visual data on methods of their hardware and software implementation is studied. A formal method for construction of architectures of vision systems for solution of different scene recognition problems which are cost-optimal for given performance is presented. Digital signal processors (DSPs) and field programmable...
This paper describes the idea of the multi-core programmable cores architecture for real-time image processing in embedded applications. The authors propose the architecture of a simple 8-bit processor core dedicated to low and intermediate level image operations. Several cores are connected to a common, 128-bit wide data bus by multiplexes and their operation is synchronized. The image data on the...
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