The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The use of virtual devices in place of physical hardware is increasing in activities such as design, testing and debugging. Yet virtual devices are simply software applications, and like all software they are prone to faults. A full system simulator (FSS), is a class of virtual machine that includes a large set of virtual devices – enough to run the full target software stack. Defects in an FSS virtual...
Using Field Programmable Gate Arrays (FPGAs) as implementation platform for systems-on-chip (SoC) has become quite popular. Typically, the software part of the system functionality is executed on a soft-core processor. Debugging such systems becomes more difficult than standard SoCs since regular debugging facilities are not always available for the processor cores and also additional hardware problems...
Open core processors allow students to explore digital design through experimentation and practice. The LEG processor described in this paper has a simple design that makes it accessible to students. The LEG processor is compatible with the ARMv5 instruction set and includes a memory management unit that allows it to boot Linux 3.19 in simulation, a combination not found in other open core processors...
In modern hardware design, substantial manual effort is required to fix a design when verification discovers a state unreachable. This paper addresses this growing pain where given an unreachable target state, a methodology is presented to return all design locations where a change can be implemented to make the target state reachable. In contrast to previous state reachability rectification techniques...
High level synthesis (HLS) tools are increasingly adopted for hardware design as the quality of tools consistently improves. Concerted development effort on HLS tools represents significant software development effort, and debugging and validation represents a significant portion of that effort. However, HLS tools are different from typical large-scale software systems; HLS tool output must be subsequently...
A complete framework and methodology to design, simulate, and debug large SoC is presented. Full VP creation using efficient tools is described. An efficient tool to allow co-debug of HW/SW on VP is also presented. The tools enable debugging and analyzing an application and a Linux driver that run on the VP. Breakpoints and mon commands can be used to detect and correct errors, access registers and...
IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview...
Common way for IP-Core standalone verification assumes UVM based environments and tests development. At the same time, IP-core integration verification at the SoC level and hardware-software co-verification as a whole, requires development of the code running on the embedded CPU (usually written on C/C++). When C/C++ tests and software are developed it is desirable to reuse IP-Core standalone level...
Multiprocessor SoCs (MPSoCs) have rapidly evolved towards high-performance heterogeneous computing systems designed under performance, power efficiency and scalability concerns. Such systems accomplish billions of operations per second moving towards hundreds of processing elements that communicate through a network-on-chip. The hardware and software complexity of such systems is increasing dramatically,...
Long gone are the days when you could use a logic analyser on a CPU to find out what it is executing. Caches, out-of-order memory accesses and especially multi-processing all effectively hide the sequence of instructions that the CPU is working on. Traditional debug techniques with breakpoints and single-stepping help, but require interactive sessions at human rates rather than the gigahertz rates...
USB forms the backbone of communication to external world. When a USB device is attached to a USB host, a sequence of interaction happens for establishing the communication channel, known as enumeration. This paper explains the enumeration process of USB2.0 in detail and discusses the challenges faced during post silicon debug of couple of issues related with enumeration. As a case study we will analyze...
Cascade is a cycle-based C++ simulation infrastructure used in the design and verification of two successive versions of Anton, a specialized machine designed for high-speed molecular dynamics computation. Cascade was engineered to address the size and speed challenges inherent in simulating massively parallel spe-cial-purpose machines. It provides a lightweight programming interface, rich debugging...
In our demonstration, we present SimXMD, a tool that enables developers to debug microcontroller code and custom hardware simultaneously. SimXMD (Simulated eXperimental Microprocessor Debugger). SimXMD connects a GNU Debugger instance to a ModelSim instance simulating an embedded FPGA system with a Xilinx Microblaze processor. We will demonstrate debugging a multiprocessor FPGA system where the processor...
Increasingly complicated VLSI design or system-on-chip (SOC) makes FPGA-based emulation necessary. As a design is downloaded into a FPGA-based emulator, invisible internal nodes of the design pose a challenge for design debugging. A debugging system is proposed to address the issue. An RTL-level runtime debugging method is utilized in the system. The user can not only select sampling signals, triggering...
With the growing size of modern designs and more strict time-to-market constraints, design errors unavoidably escape pre-silicon verification and reside in silicon prototypes. As a result, silicon debug has become a necessary step in the digital integrated circuit design flow. Although embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals...
With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide...
It is difficult to analyze and debug Cisco IOS with traditional debugging and disassembler tools such as GDB and IDA pro. These tools can't debug Cisco IOS in single step mode. This paper describes a dynamic analysis system based on a modification hardware emulator called Dynamips. Then, a new solution of inserting breakpoint with network events will be provided to analyze network communication procedures.
In this paper, we first discuss about high level formal verification and analysis techniques targeting C-based designs. They are based on dependence traversal and analyze design descriptions locally. An equivalence checking technique based on dependence traversal of the difference between the two design descriptions is shown. Then we introduce special mechanisms called patchable accelerators, for...
As the complexity of digital systems rapidly increases, designers are presented with significant challenges in monitoring, analyzing, and debugging the complex interactions of various software and hardware components. Existing hardware tests and debugging methods are often intrusive, either requiring significant hardware resources or requiring the execution of the system to be halted thus leading...
Code coverage is a popular method to find design bugs and verification loopholes. However, once a piece of code is determined to be unreachable, diagnosing the cause of the problem can be challenging: since the code is unreachable, no counterexample can be returned for debugging. Therefore, engineers need to analyze the legality of nonexistent execution paths, which can be difficult. To address such...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.