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This paper aims to show the design and prototyping of a multi-core platform that includes hardware resources to multi-core embedded processor virtualization. The virtualization process may configure the cores' address space and the association of cores to create independents groups of cores inside the platform. The platform was prototyped and validated through simulation of applications devoted to...
Exclusive last-level caches (LLCs) reduce memory accesses by effectively utilizing cache capacity. However, they require excessive on-chip bandwidth to support frequent insertions of cache lines on eviction from upper-level caches. Non-inclusive caches, on the other hand, have the advantage of using the on-chip bandwidth more effectively but suffer from a higher miss rate. Traditionally, the decision...
This paper presents a Computer Architecture Lab based on a hypothetical pedagogical computer and its corresponding software simulator designed at the University of Vigo. This computer simulator permits to access both the architecture and microarchitecture level of the computer. The paper shows the simulator features at both levels, and introduces the use of embedded core for the learning of SoC (System...
This paper focuses on the assertion-based verification (ABV) of hardware/software embedded systems, described at the Electronic System Level. We first summarize the features of a tool that enables the automatic instrumentation of SystemC TLM platforms with property checkers produced from PSL assertions and the runtime verification of these requirements. We also present its last improvements. Then...
In this paper, we address the hardware overhead of the dynamically reconfigurable functional unit (DRFU) in dynamically reconfigurable processors (DRP), in the context of low-power, embedded system-on-chips (E-SoC). We consider a tightly coupled DRP with a small, coarse-grain DRFU made of four columns of four ALUs. These are interconnected following one of the following interconnection scheme: direct...
In wireless networks, base stations are responsible for operating on large amounts of traffic at high speed rates. With the advent of new standards, as 4G, further pressure is put in the hardware requirements to satisfy speeds of up to 1 Gbps. In this work, we study the applicability and potential benefits of the IBM PowerEN processor (a multi-core, massively multithreaded platform) in the realm of...
The ARM® processor family is the most widely used 32-bit processor family, and has consistently included debug features, starting from the ARM7TDMI® processor [1]. Embedded debug forms part of the ARMv7 architecture [2]. The most recent addition to the ARM architecture family is ARMv8 [3], which represents the biggest change in the architecture's history. This paper looks at the impact of the new...
The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC...
This paper presents a micro-architectural feature in a processor's datapath to support the C language's runtime environment. A hardware accelerator for C function calls was embedded in a processor core and its impact on area and performance was evaluated. Results show that the accelerator offers a performance improvement in several different processor configurations. The performance gain depends on...
Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by means of an ad-hoc HW module connected to the address, data and control buses of the microprocessor. This module behaves as a peripheral towards...
We consider the challenges in writing efficient code for ePUMA, a novel domain-specific heterogeneous multicore architecture with SIMD DSP slave cores, multi-banked on-chip vector register files for parallel access and configurable permutation hardware that decouples memory access from computation. Suitable data layout in memory and in vector registers, combined with using ePUMA's powerful addressing...
Aiming at improving the flexibility and reducing the cost of SOC system design, the design of configurable IP core is prerequisite. In this paper, we mainly design a scalable configurable IP core and its configurable interface circuit. We call it FDP (FuDan Programmable) Configurable IP Core. This IP Core meets the requirement of configuration and scalability. Based on FDP Configurable IP Core, we...
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software...
The increasing infant mortality and wear out failure rates observed in very deep sub micron silicon technologies is now a major problem for the design of future high-density SoCs. Emerging architectures based on Multi-Processor SoCs (MPSoCs) give the opportunity to exploit the natural redundancy to control the system performance in presence of failures. In this paper we evaluate the impact of a distributed...
This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques,...
In present complex Embedded World, a large number of devices are based on embedded ×86 systems. The presence of ×86 architecture not only increases the complexity of the system but also makes the system a bit vulnerable. To overcome this weakness of embedded systems an intermediate hardware based solution is considered to be the best approach. The initiation of this work has been adapted from the...
In this paper, we present the design of a baseband System-On-Chip for tracking applications in the medical environment based on the IEEE 802.15.4 standard which can be used to track patient location in hospitals. It utilizes an ARM Cortex-M1 soft-core, 16 kb of SRAM and a bus architecture based on the AHB-Lite specification. The IEEE 802.15.4 MAC primitives are implemented in a Flash-ROM of 32 kb...
The paper presents a method for automatic RTL-interface synthesis for a given C++ function as well as for a given SystemC-interface. This task is very important in High-Level Synthesis design flow where design entry is usually done in some abstract language (e.g. C++). As a source high-level description targets different SoC architectures or protocols, so it is needed to generate relevant pin-level...
This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm...
Although code download can improve the applicable flexibility of the secure SoC, it also brings up new secure threats to the inner sensitive information and resource. In order to resist malicious code attack, the logic design of secure memory management of different levels is presented using software and hardware co-design method, and some access strategies for identification and so on are proposed...
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