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Integrating analog-to-digital converters that utilize a phase-sensitive detector (PSADCs) are frequently used in high precision instrumentation and measurement systems. As any technical object, a PSADC is subject to faults. These faults must be detected promptly and accurately by built-in low complexity hardware. In the present work, this objective is achieved by the adoption of error-control codes...
This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors...
This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the...
Hardware as well as software implementations of cryptographic algorithms are susceptible to power analysis and fault attacks. We propose a power analysis-resistant and self-checking deterministic random bit generator. The proposed structure allows a concurrent code checking and an output suppression in the case of errors.
This paper describes the technique dedicated to an analog integrated circuit testing by means of supply current monitoring. The minimal set of test points, that allows to achieve the highest possible fault coverage, is determined with the use of genetic algorithm. Thanks to the proposed dynamic scheme of phenotype coding, the optimization process is more efficient than for a standard, static genotype...
Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to single events upsets (SEUs) has been studied extensively. As transistor sizes shrink, multiple cells upsets (MCUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, built-in current sensors (BICS) or Parity codes...
The test vector generation algorithm and the compression algorithm based on general structure model of SoC was introduced in this paper. We have analyzed the PODEM algorithm for test vectors generation and translated the test pattern, and then formed the SoC general structural model test vector. Through the experimental comparison, we find the use of Golomb coding for test vector compression/decompression...
Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to Single Events Upsets (SEUs) has been studied extensively. As transistor sizes shrink, Multiple Bits Upsets (MBUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, Built-in Current Sensors (BICS) or Parity codes...
Evolutionary Computation techniques are gradually making their way into mainstream validation of complex micro-processors. In this paper, we define the validation problem within the microprocessor as well as System-on-Chip context. We also outline the evolving role of the evolutionary algorithm within the development cycle of such complex design projects. Over time, evolutionary algorithms have been...
This paper describes new compression method that is used for test pattern compaction and compression in algorithm called COMPAS, which utilizes a test data compression method based on pattern overlapping. This algorithm reorders and compresses deterministic test patterns previously generated in an ATPG by overlapping them. Independency of COMPAS on used ATPG is discussed and verified. New method improves...
Cryptographic devices have to be fully testable in order to ensure proper functionalities. On the other hand, security requirements restrict the use of some testing techniques, such as scan chains. Built-In Self Tests may be a solution, but they often require expensive additional components included into the circuitry. The possibility of using the ciphering circuit itself to perform the self test...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line. We use multiple...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
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