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Static test compaction procedures that modify tests perform the modification so as to increase the number of faults that some of the tests detect, thus making other tests unnecessary. Tests that become unnecessary are removed from the test set without reducing the fault coverage. This paper describes a static test compaction procedure of this type for transition faults that has the following additional...
Ternary reversible latches on the basis of one- and two-qutrit permutative Muthukrishnan-Stroud (MS) gates were synthesized for the first time. Such gates can be physically implemented on the basis of liquid ion-trap quantum technology. The use of adaptive genetic algorithm allowed designing the circuits of latches that are optimal with respect to quantum cost, number of gates, and delay time. Comparisons...
In digital circuit multiplier plays an important role. They are useful in many applications like arithmetic and logic unit, MAC(multiplication and accumulator) and DSP(digital signal processing).In this paper a VEDIC multiplier proposed “urdhva tiryagbhyam Multiplication” using MCLA(Modified Carry Look ahead Adder). Speed is one of the parameter of any digital circuit so to improve the speed of the...
In distributed OpenFlow controller networks, the network flow is managed by set of associated rules that are maintained by switches in their local Ternary Content Addressable Memory (TCAM) and rules are made by concerned controllers, which are local to domains. However, TACM is expensive and consumes high power. The switch inside the forwarding plane has limited TCAM space and is infeasible to maintain...
With the continuous shrinking of process technology, FinFET overpowers conventional bulk CMOS in terms of reducing Short Channel Effect's, channel control, drive strength, high ION/IOFF current ratio. So, FinFET proves to be the best alternative to cope up with the Moore's law and the current semiconductor industry needs. In this paper most active component in Digital circuits, ALU is implemented...
Reversible logic is an emerging technology with wide spread applications in the field of digital systems. The term RAM refers to memory that is accessed with an address and has latency independent of address. In semiconductor memories RAM usually refers to volatile memory read/write memory as opposed to ROM (read only memory). The 2n×2m×1 RAM has n rows and m columns, out of which one bit is selected...
Built in Logic Block Observer (BILBO) is a bank of flip-flops which are used for self-testing for complex digital IC's in pipeline approach. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Since BILBO is designed with irreversible logic gates we observe large amount of leakage power which affects its performance. So by keeping this as main criteria, our paper...
The Bluetooth Low Energy (BLE) is one of promising technologies widely used for Internet of things (IoT) services because of its low energy consumption. In IoT, BLE gateways should discover surrounding BLE devices in a short time. However, this requirement is difficult to achieve when the number of BLE devices is very large. As the number of BLE devices increase, the signal density increase, and the...
Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power 11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design were simulated...
The performance and efficiency of conventional carry skip adder structure is improved by employing increment and concatenation scheme. In the existing system the multiplier is used which consumes more power. Instead of using this structure that consists of AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) is used for skip logic. Further development in energy and speed can be achieved by the structures...
Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process one of them is array multiplier. array multiplier half adder have been used to sum the carry...
To improve the performance of reverse converter, the residue numeral system is proposed using Han-Carlson structure with excess one unit. They generate and propagate signals are transmitted to the radix tree and the data structure is used to store the strings that allows fast look up. Han-Carlson reduces the complexity and it supports the huge number of adders with high performance operation. This...
Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest...
In arithmetic operation, adder is the basic hardware unit. So adder performance affects the overall system-performance. Carry Select Adder (CSLA) is widely used in many data processors for high speed application and in digital circuits to perform arithmetic operations. The Regular Square root (SQRT) CSLA consumes more area due to the presence of two Ripple Carry Adders (RCA) in the structure. To optimize...
In two-tier heterogeneous cellular networks (HCN) where small cells are deployed overlaid with macro cells, base station (BS) association is one of the fundamental problems, which becomes even more challenging when the small cell BSs are connected to the gateways via imperfect backhaul links, e.g. using wireless technologies. In this paper, we first analyze the mean packet delay in radio access and...
Underwater Acoustic Sensor Network (UASN) is the enabling technology for a wide range of applications including naval surveillance, oil platform monitoring, earthquake forewarning, climate and ocean observation, and water pollution tracking. However, considering the enormous acoustic sensor devices and unique services of UASN, some challenges are emerging to the traditional cellular access and core...
This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any...
In recent years, home ICT services have been actively proposed. To realize the services, power consumption of sensor station increases when a sensor station often wakes up to report sensor data. In this paper, we proposed an application-aware power-saving control method for sensor stations and confirmed an effect of a proposed method which is constructed as OSGi bundle in HGW. By using the proposed...
This paper presents the modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise them in terms of power and area. In the existing Wallace multiplier architecture, the Carry Save Adder is replaced with Modified Carry Save Adder (MCSA)and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder...
Arithmetic and Logic Unit (ALU) is a critical element in a CPU and multiplier is one of the important element in the ALU. In multipliers, for reducing partial products and computing result, multi-operand adders and fast adders are required. Fast adders can be constructed by parallel prefix networks but need new design methodologies for multi-operand adders. A special structure known as counters/compressors...
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