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In this paper we describe the performance evaluation and comparison of a older "dual processor dual core AMD Opteron" server processor and a newer "single processor quad core Intel Xeon" server processor, on their performance in executing memory intensive applications. We evaluated the performance of the two micro-architectures by analyzing the results obtained from the respective...
This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for...
NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands...
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7?? high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (??SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation. Previous energy-efficient approaches usually suffer from performance degradation and redundant extension bits. In this paper, we propose a Way History Oriented Low Energy Instruction Cache (WHOLE-Cache) design for single issue and in-order execution processors. The WHOLE-Cache design not only...
The trend toward high processing power at a reasonable cost continues with the emergence of multi-core architectures with large number of cores. In such computing systems, a major technological challenge is to design the internal, on-chip communication network.This not only depends on high performance in latency, bandwidth, and fairness in contention under heavy loads, but also depends on an efficient...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
We present an architecture ideally suited for imaging and sorting large populations of single cells. Our approach combines wide-field, passive, hydrodynamic trapping of cells with active retrieval of specific single cells using radiation pressure and microfluidics. The architecture scales easily and offers single-cell resolution both with respect to imaging and manipulation, enabling sorts predicated...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track...
A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds...
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