The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This live demonstration presents a vision system based on a digital SIMD vision chip with in-pixel processing capabilities. The system is comprised of asynchronous/synchronous processor array (ASPA2), embedded custom microcontroller with interface circuits and software development environment. Execution of a number of low and medium level image processing algorithms in real time is demonstrated.
This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The...
This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized...
In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) - a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are discussed. At 75 MHz ASPA2 demonstrates 373 GOPS/W...
Emerging 3D-integration enables integrating high quality image sensors with various massively parallel processing elements. Analog motion estimation is one potential application, which is likely to result in significant benefits in the form of low power or high frame-rate 3D-integrated image sensor-processors. The system-level operation of a proposed analog motion estimation array, enabling all various...
Displacement calculation algorithm is implemented on a heterogeneous sensor processor architecture, constructed of a mixed signal medium resolution processor array, and a digital, low resolution, foveal processor array. The algorithm is designed as an initial step of an airborne navigation framework. It features multi-scale multi-fovea processing.
This paper presents an implementation of object segmentation and tracking with asynchronous grayscale and binary wave operations on the MIPA4k processor array. Measured examples of applications of grayscale and binary processing based on asynchronously propagating wave-type operations are shown.
Current research is mainly focussing on exploiting TLP to increase performance. Another avenue, however, for achieving performance scalability is specialization. In this paper we propose application specific intra-vector instructions for two dimensional signal processing kernels. In such kernels usually significant data rearrangement overhead is required in order to use the SIMD capabilities. When...
This paper presents an implementation of locally adaptive image sensing with the MIPA4k image processor array. The implemented adaptive sensor circuitry allows the extraction of image detail in the presence of large dynamic intra-scene lighting variations. The implemented circuit method is based on the use of nonlinear resistive network filtering during image integration for controlling the pixel...
Massively deployed inside Sony PS3 platforms, the STI Cell Broadband Engine is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). In this paper, we describe three image processing applications which we implemented on the Cell BE. We report the performance measured on one Cell blade with varying numbers of synergic processor engines enabled, and with...
2D operators were categorized based on their implementation methods on different low-power topographic and non-topographic single-chip processor architectures. The implementation methods of the 2D operators in the individual categories are shown, and their processor utilization efficiency is analyzed. The execution times of the basic operators on the different architectures are calculated, the power...
In this paper, a testable 2-D motion estimation (TME) design at the bit level (TMEbit) based on the C-testability conditions are proposed. In order to meet the testability conditions, the bit-level cell functions are made bijective. Our C-testability conditions guarantee about 100% fault coverage for single cell fault model with a constant number of test patterns. The number of test patterns is 128...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.