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In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its...
An external capacitor-less low dropout (LDO) voltage regulator with high PSRR and enhanced transient response is presented. The novel idea is applying a replica circuit which can pull excessive current. Excessive Current Pulling (ECP) technique decreases the equivalent output impedance to enhance transient response. The proposed LDO has been simulated in 0.18 μm CMOS Technology. Its regulated output...
A novel structure of current controlled negative resistance is presented in this paper. It has a very useful role in many analog circuits like oscillators and bandpass filters. The negative resistance circuit, which requires no external passive component, is constituted of two simplified negative second generation current controlled conveyors (CCCII−). This conveyor uses NPN bipolar transistors to...
This paper demonstrates the design and simulation of input matching circuit for BLF578XR power transistor working at center frequency of 225 MHZ with bandwidth of more than 50 MHZ. Based on the calculated Q-factor and when using the transistor in push pull mode, the input matching circuit is designed in two stages, the first stage is a balun to match 50 ohm to 12.5 ohm and the other stage is to match...
This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
In this paper, a low-noise amplifier (LNA) designed for the lower band of the ultra-wideband (UWB) spectrum and implemented in 0.18 μm CMOS process is presented. Post-layout simulations show a power gain (S21) of 11.18 dB with 0.8 dB value variations from 259 MHz to 5 GHz. The input and output return losses, S11 and S22, are below −10 dB from 466.4 MHz to 5.63 GHz, while reverse isolation (S12) is...
In this paper, a modified structure for low-swing voltage-mode drivers in high-speed serial links is proposed. A dynamic current-driven bulk-biasing technique is applied to the driver transistors to achieve proper channel impedance termination and to minimize the transistors' sizes. Simulation results of an 8-Gb/s serial link in all process corners of a 0.13-μm CMOS technology confirm that, by using...
In this paper, a new design for current comparator based on Current Conveyor-II (CC-II) is proposed. The proposed current comparator utilizes the concept of positive feedback. Simulations have been performed on Pspice using 0.18um CMOS technology with 1.8V supply. Final results confirm a fairly quick response, less power dissipation and a resolution of 4.4uA for the current comparator. A 2-bit current...
Recent advances in technology have driven renewed interest in the design of CMOS negative capacitance circuits for diverse applications such as wideband metamaterials and radio frequency integrated circuits. In practice, the particular CMOS fabrication process generally limits the practical range of capacitance values and bandwidths that can be achieved. In addition, the reactive component of the...
This paper presents a front-end circuit for electrochemical biosensors used in applications like DNA sensing. Novelty in this work lies in the front-end architecture which uses noise canceling (NC) combined with chopper stabilization (CS) for rejecting 1/ƒ noise and to our knowledge, a front-end using the principle of noise canceling for 1/ƒ noise rejection has not been reported. Motivation for using...
This paper proposes a novel complementary current approach to eliminating the code-dependence in the output impedance of current-steering digital-to-analog converters (DACs), and increasing the spurious-free dynamic range (SFDR) significantly. A 14bit 1.0GS/s current-steering DAC design example shows an SFDR increase of 10∼15dB. In traditional designs, one major effect that degrades the linearity...
In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared...
A bandgap voltage reference is designed in this paper with very low power consumption in 0.18 mum Bi-CMOS process. A voltage-current converter is also designed to provide a current reference of 400 muA in 0.18 mum Bi-CMOS process. This new proposed current reference can work properly for output voltage in a wide range between 0.2 V to 1.6 V with output impedance greater than 12.5 kohms. The output...
CMOS pseudo differential operational transconductance amplifier (OTA) has been proposed in this study. It can operate with significantly low supply voltage and provides respectable high output impedance. Besides, it enhances the common mode rejection ratio (CMRR) by using a special common mode feed forward (CMFF) technology. The chip has been manufactured in a 0.35 ??m-CMOS technology. The simulation...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
Wideband, self-biased, second generation current conveyor (CCII) is proposed. It is shown that the proposed CCII exhibits superior performance compared to its previous counterparts in terms of bandwidth, parasitic resistance and voltage swing on port X. Also, the proposed CCII uses no additional biasing voltage or current sources other than the two supply rails.
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