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Chaotic systems can be used for secure communication such as transmitting video, audio and text files. Various chaotic generators have been implemented on FPGA in realtime for synchronous communication applications. In this paper, a detailed design approach is presented to implement modelbased chaotic generator designs on FPGA. Henon map has its significance in studying chaotic systems and is used...
Since decades, orthogonal frequency division multiplexing (OFDM) has been drawing its attention in the area of wireless and satellite communication systems such as IEEE 802.11 a/g/n, ADSL, WiMAX and DVB-T/SH. In these applications, OFDM has drawbacks of high Peak-to-Average Power Ratio (PAPR) and Inter carrier symbol interference (ISI). Recently, Carrier Interferometry OFDM (CI-OFDM) as an alternative...
A5/1 and A5/2 are the GSM encryption algorithms that protect user data transmission over air. However, both of the A5/1 and A5/2 were cryptanalized by using different attack techniques such as time-memory trade off, divide and conquer and correlation attacks. In this study, we present a modified version of the A5/1 and A5/2 with offering security improvements to the vulnerabilities of the algorithms...
Salphasic (literally phase saltation) distribution assumes the creation of a standing wave pattern in the clock distribution network in such a way as to present an amplitude anti-node to the driving circuit. A characteristic of standing wave patterns is the existence of extended constant-phase regions (of a length of half-wavelength), with abrupt changes of 180 degrees at the amplitude nodes. These...
A path generator is proposed for a fixed-wing Unmaned Aereal Vehicle (UAV). Assuming that the vehicle maintain a constant altitude, and airspeed, and that the UAV is constrained by a turning rate. The Dubins paths serve as a strategy to find the shortest path for the non-holonomic model of the UAV. Dubins paths consist of three path segments which are based on straight lines or arcs of circle of a...
Resonant clocking is a promising low power alternative for conventional clocking method. In this work, a design methodology is presented for square wave resonant clocking technique to assure minimum power consumption. These equations were verified by designing a differential clock generator which showed 55% power savings compared to conventional clocking.
This paper presents a real-time simulation of a sensorless control method for IPMSM drives based on Park Transformation with a reference frame fixed to the rotor and assuming a sinusoidal flux (sinusoidal back-emf). The objective of this paper is to Hardware In Loop (HIL) evaluation of a sensorless position estimation of the Permanent Magnet Synchronous Motor (PMSM) drive at standstill as well as...
PingPong-128 stream cipher is a 128 bit key stream generator with 257 internal states. It provides irregular clocking by mutual clock control mechanism and hence, provides significant immunity against existing attacks. However, hardware implementation of PingPong-128 is also essential for fast ubiquitous application. This paper proposes an FPGA based hardware implementation of PingPong-128 stream...
Fine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each voltage/ frequency island must be taken into account to optimize the circuit. This paper focuses on the control for the frequency actuator. An optimal and robust saturated...
Feedback with Carry Shift Registers (FCSRs) are being explored as a potential replacement of Linear Feedback Shift Registers (LFSRs) in the design of stream ciphers. Many cryptographic schemes based on FCSRs have been proposed in the open literature. The most efficient attack against ciphers based on FCSRs are ‘linearisation attacks’, which consists of three variants, namely ‘Conventional Linearisation...
This paper focuses on a new pipelined processing unit architecture dedicated to mixed-signal power system emulation. Prior research in this field has proven that analog emulation overcomes the speed limits of numerical simulators with reliable accuracy. Then, a new concept based on field programmable power network system (FPPNS) has been developed in order to gain in term of flexibility. It is based...
A detailed analytical approach is proposed to determine the required driver strength in the resonant clock generator. The proposed approach reduces area and power overhead by eliminating the need to have switches with programmable widths and reference pulses with programmable duty cycles. Simulation results show accurate estimation of the required driver strength at short pulse widths. However, as...
Spike based imagers commonly use either time-to-first spike (TTFS) or spike rate encoding exclusively. In this paper we discuss the benefits of using a mixed-mode encoding scheme backed by theoretical analysis and SPICE simulations. The mixed-mode readout uses both TTFS and spike rate information to estimate the illumination for each pixel, which lessens the maximum spike rate and timing clock speeds...
This paper presents a hardware design for a scalable, high throughput, configurable LFSR. High throughput is achieved by producing L consecutive outputs per clock cycle with a clock cycle period that, for practical cases, increases only logarithmically with the block size L and the length of the register N. Flexibility is ensured by offering full reconfigurability of the generator polynomial within...
A visual polychronous formalism called Multi-Rate Instantaneous Channel Connected Data Flow (MRICDF)was developed in. In, a visual environment called EmCodeSyn was introduced which performs software synthesis from MRICDF models. The synthesis technique replaced clock calculus technique germane to previous polychronous approaches such as SIGNAL with a top down technique based on computing the Prime...
The paper deals with true random number generators using a set of ring oscillators as proposed by Sunar et al. in 2007. The original generator has been recently enhanced by Wold and Tan by introducing flip-flops at the output of each ring. We show in the first part of the paper that both original and enhanced architectures have exactly the same behavior when composed of ideal components (they have...
Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances, and switching frequencies. Energy-recovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation...
In this paper, the concept of the discrete unitary transforms induced by given signals or input signals is modified and developed. The basic transformations composing such transforms are parameterized and the energy (or its partial part) of signals is transferred to one of their components in different paths. We focus on the case when all basic transformations themselves represent Givens rotations...
Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
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