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This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using TCC(Threshold Configuring Comparator) for the 5 MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um × 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling...
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-µm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the...
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate...
A CMOS capacitor-free low-dropout (LDO) voltage regulator with 0.65-1.8 V power supply is presented. Positive feedback is used to build the differential computation of the error amplifier and the positive feedback gain is less than unity to ensure the stability. The LDO is designed in TSMC 0.18 μm CMOS processes. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The simulation...
This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more...
In this paper, an ultra-low power biopotential acquisition system is presented. The proposed system contains a tunable band-pass amplifier, a VGA with strong capacitive driving capability and a successive approximation ADC. To make the gain and bandwidth programmable, a T-switch with huge cut-off resistor is utilized to eliminate the effect of low frequency doublets. An improved low kick-back noise...
A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to 35-MS/s using a pipelined architecture in a CMOS 0.35 m process. The first front-end stage of 2.5 bits includes an efficient dynamic element matching scheme permitting to average its gain errors. The back-end converter is a...
In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
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