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The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the...
In this paper the simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register (SAR) analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the...
In present work is carried out modelling of single transistor parallel ZVS DC-DC converter. Main advantage of power circuit is direct work in steady mode. Thus, that allows avoiding a starting procedure and guarantees reliable operation in significant major change in load occur. The model is realised with Matlab. Computer simulations and experiments in lab model are performed by which the model is...
In this paper a design of two-stage CMOS operational amplifier for sigma-delta ADC is presented, which operates at ±1.8 V power supply using 180 nm technology. This two-stage CMOS OP-AMP has been designed to indicate a unity gain frequency of 18.2MHz and indicates a gain of 71.27 dB. The design and simulation part has been done on Cadence Custom IC CAD. The simulated results are encouraging and has...
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-µm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the...
A novel aperture error reduction technique for subrange successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. By reusing capacitors of flash ADC during fine conversion phase, thermometer coarse capacitors belonging to CDAC can be removed from the circuit. Compared with the conventional subrange SAR ADC without front-end T/H, this technique can minimize...
In this paper, a new active-only integrator which can be used to realize low frequency filters with small chip area is presented. The circuit can be effectively implemented using transconductance elements and its integration frequency is electronically controllable. In order to illustrate its usefulness, a second-order multifunction filter with low cut-off frequency, yet which occupy a small chip...
In this paper, a new coupling circuit is presented. This circuit uses a new method of subthreshold region biasing to decrease the value of coupling capacitor. In proposed circuit the Coupling capacitor is decreased about 98% in comparison with the ordinary capacitive coupling circuit. In addition, the proposed coupling circuit achieves higher linearity. The performance evaluation of proposed circuit...
This paper presents the full zero voltage switching three-level boost dc-dc converter. The boundary conduction mode and snubber capacitors provide zero voltage switching operation in the whole range of operation. Analytical estimation and simulation results have proved the proposed idea. In advance, it was demonstrated that the multi-cell structure along with an interleaved control technique provide...
In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal....
In this paper, an electronically tunable current-mode quadrature oscillator employing three current follower trans-conductance amplifiers (CFTAs) and two grounded capacitors is proposed. The use of all grounded capacitors makes the proposed circuit ideal for integrated circuit implementation. The circuit provides two high-output impedance current signals with 90° phase difference. It condition of...
This paper presents modeling, design and analysis of a bidirectional half-bridge DC/DC converter suitable for power electronic interface between the main energy storage system and the electric traction drive in hybrid electric vehicles. A hybrid energy storage system composed of a battery unit and an ultracapacitor pack is considered. A parallel dc-linked multi-input converter with a half-bridge bidirectional...
A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies...
This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier...
This article presents a low-power low-noise neural recording system comprising a set of 4-channel amplifiers and a dual-threshold adaptive action potential detector. The front-end amplifier is optimized for power efficiency, noise, and silicon area. A balanced tunable pseudo-resistor is used to acquire local field potential (LFP) and action potential (AP) separately. The post-layout simulation results...
A low power smart temperature sensor followed by an SC amplifier, buffer stage and a 12bit Successive-Approximation analogue-digital converter (ADC) for autonomous multi-sensor systems is presented. The proposed design is accurate within 0.1°C over the temperature range of −55°C to 125°C. A PTAT source like the one presented in [1] was used as a high accuracy temperature sensor. The read-out enables...
A compact biphasic neural stimulator for use in multi-channel integrated neural recording and stimulation interfaces is presented. The stimulator is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The stimulator reuses the capacitive DAC inside the recording SAR ADC to provide 8-bit current amplitude resolution and reconfigures the digital SAR controller...
A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The proposed charge pump is overstress free and compatible...
Single Photon Avalanche Diodes (SPADs) create a very short duration voltage pulse whenever a photon is detected. The resulting high sensitivity and temporal resolution makes them useful in a range of applications. In this paper two different analogue circuits are reported that are suitable for imaging applications that can record the number of detected photons in the limited area available between...
This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32 nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the proposed...
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