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This paper presents a new asynchronous binary search analog to digital converter (ADC). Proposed asynchronous binary search ADC enables higher speed operation of binary search algorithm by resolving two bits in each step. Using two bit flash quantizers in each stage of the proposed binary search ADC the conversion speed improves by two times compared with conventional binary search ADC architectures...
This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly...
This paper presents the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. An analogy between the Kalman filter and a linearized BB CDR is utilized for the derivation. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of the...
Serial link interconnection has generated a lot of attention in on-chip bus design due to its advantages over multibit parallel interconnection in terms of crosstalk, skew, and area cost. However, serializing a multi-bit parallel bus tends to increase the bit transition and power dissipation. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between...
In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18??im CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed elaborately. The total area including I/O...
Sine-shaping of feedback DAC current in continuous-time ΣΔ ADCs is an effective solution to enhance their immunity to clock jitter. In this paper, a simple mixer circuit for producing a sine-shaped output in continuous-time ΣΔ ADCs is introduced. The proposed solution does not need extra clock source or synchronization circuit, as the mixer utilizes the same clock applied to the comparator. It is...
In the majority of the digital designs, adder is the basic building block of the most computational systems. Recently, increasing the speed of adders has been a challenging issue for most of researchers. In this article, a developed adding method is proposed for half adder (HA) based pipeline adders where the output evaluating and latching operations are combined together. As the output functions...
Traditional Delay-Locked-Loop (DLL) method can be hardly used in high-rate Direct-Sequence Ultra-Wideband (DS-UWB) systems due to dense multipath environment, low spreading factor and high-frequency clock. Most of the existing researches on tracking in UWB scenario focus on low-rate Impulse-Radio UWB (IR-UWB). In this paper, a non-Numerical Controlled Oscillator (NCO) periodical-pilot-assisted tracking...
Irregular routing algorithms, as modified if fault tolerant algorithms, can be utilized by irregular networks. These algorithms conventionally use several virtual channels (VCs) to pass faults and oversized nodes. In this paper, a new wormhole-switched routing algorithm for irregular 2-D mesh interconnection Network-on-Chip is proposed, where no VC is used for routing. We also improve message passing...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are based upon UMC 0.13μm CMOS process at 1.2 V...
Tracking constitutes a major challenge in Ultra-Wideband (UWB)communications due to dense multipath environment and low power consumption. Most of the existing studies on tracking fall within low rate Impulse Radio UWB (IR-UWB) scope, with the assumption that Inter-Frame Interference (IFI) or Inter-Symbol Interference (ISI) is absent. In this paper, we settle on high rate Direct-Sequence UWB (DS-UWB)...
An all digital delay-locked loop (ADDLL) with "reset in every step" (RES) delay line is developed in order to reduce the locking time. Due to the novel resettable mechanism of delay line, the DLL has the property of fast-locking and harmonic-free. The locking time can be reduced to N+1, where N is the bits' number of the control code for a delay line. According to the simulation result in...
The purpose of this work is to add one more circuit into the PLL to define the lock condition. New types of PLL lock detectors, the principles of their operation, parametrical comparisons are presented. Presented circuits provide a simple design and independence from supply voltage (analog lock detector) or design automation (fully digital lock detector).
Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization...
Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation.
In the automotive domain, several loosely-coupled architecture description languages (ADLs) compete to provide a set of abstract modeling and analysis services on top of the implementation code. In an effort to make all these languages, and more importantly their underlying models, interoperable, we use the UML profile for MARTE as a pivot to define the semantics of these models.In this paper, we...
Power consumption is a critical design issue in embedded processor design. One of common components in the processor is the Arithmetic and Logic Unit (ALU). Usually, ALUs are designed with a combinational logic circuit containing a number of functional components for different arithmetic and logic operations. An ALU can be constructed with a tree or a chain structure. Existing approaches to reduce...
Automatic generation of code starting from lightweight modeling languages such as UML is by now a widely adopted approach. In particular generation of executable SystemC models starting from StateCharts and other UML diagrams represents a promising research field. While RTL SystemC appears better suited for matching the StateCharts formalism (being intrinsically clocked), performances of the generated...
4-bit 2-Gsample/s flash A/D converter is presented. It is realized in a digital 0.13 um CMOS technology. To compensate for timing skew and delay problem at comparator outputs, a new latched-skewed-logic is introduced; the proposed latched-skewed-logic improves the performance of the A/D converter with negligible increase in power consumption. The simulation results show that the implemented A/D converter,...
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