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Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
A glitch compensation methodology is proposed in this paper which involves reducing the undesired switching of selected combinational cells from a place and routed standard cell layout in order reduce peak dynamic voltage or IR drop. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that occurs before intended value in digital...
The HSPA mobile wireless technology is now widely used and is expected to gradually converge with next-generation broadband technologies. As such, 3GPP focuses on HSPA advances beyond Release 10 including “Further Enhancements to CELL_FACH”. In CELL_FACH state, the UE can transmit smaller amounts of data, while taking advantage of significantly less power consumption. Recently, the usage of CELL_FACH...
This paper presents a new asynchronous binary search analog to digital converter (ADC). Proposed asynchronous binary search ADC enables higher speed operation of binary search algorithm by resolving two bits in each step. Using two bit flash quantizers in each stage of the proposed binary search ADC the conversion speed improves by two times compared with conventional binary search ADC architectures...
A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay...
For sensor networks, the extension of operating time by controlling power consumption is an important research subject. In a receiver-driven communication protocol, a receiver node transmits its ID to the sender node periodically, and in response the sender node sends an acknowledgment. The average power consumption of the network can be controlled, but a part of the network shuts down when the battery...
In this paper we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to...
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation...
Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of...
We numerically analyze the performance of the emerging 802.16 m's sleep mode operation in order to gain a new insight regarding its power consumption and traffic transmission delay when a Mobile Station (MS) in the sleep mode is served with both non-realtime and realtime traffic simultaneously. We validate the analysis via the comparison with simulation results.
Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation.
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
Power consumption is a critical design issue in embedded processor design. One of common components in the processor is the Arithmetic and Logic Unit (ALU). Usually, ALUs are designed with a combinational logic circuit containing a number of functional components for different arithmetic and logic operations. An ALU can be constructed with a tree or a chain structure. Existing approaches to reduce...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
In this paper, an energy efficient adaptive modulation scheme is proposed for a wireless cognitive radio ad hoc network, where each node is equipped with cognitive radio and the network is an OFDMA system operating on time slots. In each slot, the users with new traffic demand will sense the spectrum and locate the available subcarrier set. Then they choose subcarriers with favorable channel condition...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
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